公开(公告)号：US06225818B1

公开(公告)日：2001-05-01

申请号：US09304030

申请日：1999-05-03

Applicant: Cheol-hong Park ,  Sang-seok Kang ,  Jae-hoon Joo

Inventor： Cheol-hong Park ,  Sang-seok Kang ,  Jae-hoon Joo

IPC: G01R3102

CPC classification number: H01L23/544 ,  G01R31/2884 ,  G06F11/006 ,  H01L2223/5444 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes first and second pads that are electrically connected to a circuit inside the integrated circuit. The circuit performs multiple functions which may be selected. A function identification circuit, inside the integrated circuit, is electrically connected to the first and second pads. The function identification circuit operates in multiple modes, wherein each operating mode corresponds to a function performed by the circuit. The function of the circuit may thereby be identified using fewer pads which may allow a reduction in the cost of the integrated circuit.

Abstract translation: 集成电路包括电连接到集成电路内的电路的第一和第二焊盘。 电路执行可以选择的多种功能。 集成电路内部的功能识别电路电连接到第一和第二焊盘。 功能识别电路以多种模式工作，其中每个操作模式对应于由电路执行的功能。 因此，可以使用更少的焊盘来识别电路的功能，这可以允许降低集成电路的成本。

公开(公告)号：US06111457A

公开(公告)日：2000-08-29

申请号：US44382

申请日：1998-03-18

Applicant: Jong-Hyoung Lim ,  Sang-Seok Kang ,  Jae-Hoon Joo ,  Chang-Joo Choi

Inventor： Jong-Hyoung Lim ,  Sang-Seok Kang ,  Jae-Hoon Joo ,  Chang-Joo Choi

IPC: G11C11/413 ,  G05F1/46 ,  G05F3/24 ,  G11C5/14 ,  G11C11/407 ,  H01L21/822 ,  H01L27/04 ,  G05F3/02

CPC classification number: G05F1/465

Abstract: An internal power supply circuit for use in a semiconductor device includes a clamp circuit for clamping an internal voltage to a constant level. The clamped internal voltage is distributed to internal circuits of the semiconductor device through an output node. When the internal voltage rises momentarily due to noise in the internal power supply circuit due to open-circuit phenomenon, the rising internal voltage is discharged through the clamp circuit, thereby maintaining the internal voltage at a constant value. The clamp circuit includes a first transistor for discharging the output node, and a diode-connected transistor for generating a charge voltage at the gate of the first transistor. The threshold voltage of the diode-connected transistor is preferably equal to or lower than the threshold voltage of the first transistor.

Abstract translation: 用于半导体器件的内部电源电路包括用于将内部电压钳位到恒定电平的钳位电路。 被钳位的内部电压通过输出节点分配给半导体器件的内部电路。 当内部电压由于开路现象而由于内部电源电路中的噪声而瞬间上升时，内部电压的上升通过钳位电路放电，从而将内部电压保持在恒定值。 钳位电路包括用于对输出节点放电的第一晶体管和用于在第一晶体管的栅极处产生充电电压的二极管连接的晶体管。 二极管连接晶体管的阈值电压优选等于或低于第一晶体管的阈值电压。

公开(公告)号：US5929696A

公开(公告)日：1999-07-27

申请号：US953052

申请日：1997-10-17

Applicant: Jong-Hyoung Lim ,  Jae-hoon Joo ,  Sang-seok Kang ,  Jin-seok Lee

Inventor： Jong-Hyoung Lim ,  Jae-hoon Joo ,  Sang-seok Kang ,  Jin-seok Lee

IPC: G11C11/413 ,  G05F1/46 ,  G11C11/401 ,  G11C11/407 ,  G11C29/06 ,  H01L27/10 ,  G05F1/10

CPC classification number: G05F1/465

Abstract: An internal voltage conversion circuit for a DRAM wherein a voltage level of an internal power supply is regulated by an external signal applied to the DRAM pins after packaging to perform reliability tests. The internal voltage conversion circuit includes a test mode signal generator, for generating a test mode signal by combining first control signals applied externally of the semiconductor device, and a switching signal generator, for generating first and second switching signals according to second control signals applied externally of the DRAM when the test mode signal is active. First and second switching resistor portions connected in series between the internal power supply port and a ground potential are switched by the first and second switching signals, respectively, so that their resistance values are changed. The resistor portions are in a feedback path connected to one input of a comparator. The other input is connected to a reference cell. The internal voltage supply varies responsive to changes in resistance values.

Abstract translation: 一种用于DRAM的内部电压转换电路，其中内部电源的电压电平通过在封装之后施加到DRAM引脚的外部信号进行调节以执行可靠性测试。 内部电压转换电路包括测试模式信号发生器，用于通过组合在半导体器件外部施加的第一控制信号和开关信号发生器产生测试模式信号，用于根据外部施加的第二控制信号产生第一和第二开关信号 当测试模式信号有效时。 串联连接在内部电源端口和接地电位之间的第一和第二开关电阻部分分别通过第一和第二开关信号切换，使得它们的电阻值被改变。 电阻器部分处于连接到比较器的一个输入端的反馈路径中。 另一个输入连接到参考单元。 内部电压供应根据电阻值的变化而变化。

公开(公告)号：US08228736B2

公开(公告)日：2012-07-24

申请号：US12591976

申请日：2009-12-07

Applicant: Jae Hoon Joo ,  Sang Seok Kang ,  Jong Hyoung Lim

Inventor： Jae Hoon Joo ,  Sang Seok Kang ,  Jong Hyoung Lim

IPC: G11C16/04

CPC classification number: G06F1/206 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40626 ,  G11C2211/4067

Abstract: A mobile System on Chip (SoC) comprises a microprocessor and a first memory controller configured to control a refresh of a first memory. A temperature sensor detects a temperature in the first memory. When first temperature information received from the temperature sensor indicates that the detected temperature deviates from a predetermined temperature range, the first memory controller controls the first memory so as not to perform a self refresh. When second temperature information received from the temperature sensor indicates that the detected temperature is in the predetermined temperature range, the first memory controller outputs a self refresh command to the first memory.

Abstract translation: 移动片上系统（SoC）包括微处理器和被配置为控制第一存储器的刷新的第一存储器控制器。 温度传感器检测第一存储器中的温度。 当从温度传感器接收到的第一温度信息指示检测到的温度偏离预定温度范围时，第一存储器控制器控制第一存储器以便不进行自刷新。 当从温度传感器接收到的第二温度信息指示检测到的温度处于预定温度范围时，第一存储器控制器向第一存储器输出自刷新命令。

公开(公告)号：US20100034031A1

公开(公告)日：2010-02-11

申请号：US12461277

申请日：2009-08-06

Applicant: Sang-Seok Kang ,  Hyung-Dong Kim

Inventor： Sang-Seok Kang ,  Hyung-Dong Kim

IPC: G11C5/14 ,  G11C7/00 ,  G11C7/02

CPC classification number: G11C11/406 ,  G11C5/147 ,  G11C11/40615 ,  G11C11/4074 ,  G11C2211/4068

Abstract: A semiconductor memory device includes a voltage level selection unit configured to output a plurality of voltage level selection signals according to a fuse program in response to a self-refresh command signal and a reference voltage generator configured to receive a reference voltage and output a target reference voltage having a different voltage level depending on a normal mode or a self-refresh mode in response to the voltage level selection signals.

Abstract translation: 半导体存储器件包括：电压电平选择单元，被配置为响应于自刷新命令信号，根据熔丝程序输出多个电压电平选择信号;以及参考电压发生器，被配置为接收参考电压并输出目标参考 响应于电压电平选择信号，具有取决于正常模式或自刷新模式的不同电压电平的电压。

公开(公告)号：US07569904B2

公开(公告)日：2009-08-04

申请号：US11177242

申请日：2005-07-08

Applicant: Boa-Yeong Oh ,  Sang-Seok Kang ,  Kyoung-Moo Kim

Inventor： Boa-Yeong Oh ,  Sang-Seok Kang ,  Kyoung-Moo Kim

IPC: H01L31/058

CPC classification number: H03K19/00369

Abstract: A semiconductor device comprises a plurality of banks, a plurality of control circuits, and a plurality of temperature sensors, wherein each of the plurality of temperature sensors is disposed near at least one of the plurality of banks for sensing the temperature of the area surrounding the at least one of the plurality of banks and for outputting a sense signal corresponding to a sensed temperature, and each of the plurality of control circuits outputs at least one control signal, for controlling an operation of the at least one of the plurality of banks, to the at least one of the plurality of banks based on the sense signal.

Abstract translation: 半导体器件包括多个堤，多个控制电路和多个温度传感器，其中多个温度传感器中的每一个设置在多个堤中的至少一个堤附近，用于感测围绕该区域的区域的温度 所述多个存储体中的至少一个并且用于输出对应于感测温度的检测信号，并且所述多个控制电路中的每一个输出至少一个控制信号，用于控制所述多个存储体中的至少一个存储体的操作， 基于感测信号到多个存储体中的至少一个存储体。

公开(公告)号：US07483320B2

公开(公告)日：2009-01-27

申请号：US11266154

申请日：2005-11-03

Applicant: Sang-Man Byun ,  Soo-In Cho ,  Sang-Seok Kang

Inventor： Sang-Man Byun ,  Soo-In Cho ,  Sang-Seok Kang

IPC: G11C7/00 ,  G11C29/00

CPC classification number: G11C29/48 ,  G11C29/1201

Abstract: In a method of inputting/outputting data in a semiconductor memory device, first data and second data are buffered and outputted to a first output node and a second output node, respectively, in a normal mode. In a test mode, the first data is buffered through a first transmission line and a second transmission line and outputted to the first output node and the second output node in response to at least one control signal. Also, in the test mode, the second data is buffered through the first transmission line and the second transmission line and outputted to the first output node and the second output node in response to the at least one control signal. Accordingly, test time may be reduced, and variations of operation characteristics caused by merging the data pins may also be reduced.

Abstract translation: 在半导体存储器件中输入/输出数据的方法中，第一数据和第二数据被缓冲并分别以正常模式输出到第一输出节点和第二输出节点。 在测试模式中，第一数据通过第一传输线和第二传输线进行缓冲，并响应于至少一个控制信号被输出到第一输出节点和第二输出节点。 此外，在测试模式中，第二数据通过第一传输线和第二传输线缓冲，并且响应于至少一个控制信号被输出到第一输出节点和第二输出节点。 因此，可以减少测试时间，并且还可以减少由数据引脚合并引起的操作特性的变化。

公开(公告)号：US07466616B2

公开(公告)日：2008-12-16

申请号：US11498721

申请日：2006-08-04

Applicant: Sang-Man Byun ,  Sang-Seok Kang ,  Jong-Hyoung Lim

Inventor： Sang-Man Byun ,  Sang-Seok Kang ,  Jong-Hyoung Lim

IPC: G11C7/02

CPC classification number: G11C11/4091 ,  G11C7/08

Abstract: A bit line sense amplifier and method thereof are provided. The example bit line sense amplifier may include a sense amplifying circuit coupled between a first bit line and a second bit line. The sense amplifying circuit may be configured to amplify a voltage difference between the first bit line and the second bit line. The example bit line sense amplifier may further include a power supply voltage providing circuit configured to provide a first power supply voltage and a second power supply voltage to the sense amplifying circuit in response to first and second bit line sensing control signals. The bit line sense amplifier may further include a bit line voltage compensation circuit configured to prevent a voltage-reduction at the first bit line and the second bit line for a delay period, the delay period including at least a period of time after a pre-charging of the first and second bit lines, in response to one or more of the first and second bit line sensing control signals.

Abstract translation: 提供了位线读出放大器及其方法。 示例性位线读出放大器可以包括耦合在第一位线和第二位线之间的读出放大电路。 感测放大电路可以被配置为放大第一位线和第二位线之间的电压差。 示例性位线读出放大器还可以包括电源电压提供电路，其被配置为响应于第一和第二位线检测控制信号向感测放大电路提供第一电源电压和第二电源电压。 位线读出放大器还可以包括位线电压补偿电路，配置为在延迟时段内防止在第一位线和第二位线处的电压降低，该延迟周期至少包括预处理后的一段时间， 响应于第一和第二位线感测控制信号中的一个或多个，对第一和第二位线进行充电。

公开(公告)号：US07075854B2

公开(公告)日：2006-07-11

申请号：US10927142

申请日：2004-08-27

Applicant: Sei-Hui Lee ,  Sang-Seok Kang

Inventor： Sei-Hui Lee ,  Sang-Seok Kang

IPC: G11C8/00

CPC classification number: G11C29/12015 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/12 ,  G11C29/12 ,  G11C2029/1204 ,  G11C2207/002

Abstract: A semiconductor memory device and a write control circuit which may detect write failures and a write control method for the same are provided. The semiconductor memory device may include a memory cell array, a bit line amplifier, a switch unit, and a write driver. Exemplary embodiments of the semiconductor memory device, according to the present invention, may determine the activation timing of the column select line signal using a clock enable signal and a mode register set signal, without synchronizing with a master clock signal.

Abstract translation: 提供了可以检测写入失败的半导体存储器件和写入控制电路以及用于其的写入控制方法。 半导体存储器件可以包括存储单元阵列，位线放大器，开关单元和写入驱动器。 根据本发明的半导体存储器件的示例性实施例可以使用时钟使能信号和模式寄存器设置信号来确定列选择线信号的激活定时，而不与主时钟信号同步。

公开(公告)号：US20060114731A1

公开(公告)日：2006-06-01

申请号：US11327104

申请日：2006-01-05

Applicant: Choong-Sun Park ,  Hyung-Dong Kim ,  Sang-Seok Kang ,  Jong-Hyun Choi ,  Yong-Hwan Jung

Inventor： Choong-Sun Park ,  Hyung-Dong Kim ,  Sang-Seok Kang ,  Jong-Hyun Choi ,  Yong-Hwan Jung

IPC: G11C7/06 ,  G11C5/14

CPC classification number: G11C5/145 ,  G11C5/146 ,  G11C29/006 ,  G11C29/02 ,  G11C29/021 ,  G11C29/12005 ,  G11C29/1201

Abstract: The invention relates to a method and apparatus for controlling a high voltage generator during wafer burn-in. The method includes generating an enable signal for enabling a high voltage generator responsive to a mode signal, e.g., a wafer burn-in test mode. The method provides an external voltage to a semiconductor memory device through a pad responsive to the enable signal. The method varies a high voltage level being output from the high voltage generator in response to a reference voltage level.

Abstract translation: 本发明涉及一种用于在晶片老化期间控制高压发生器的方法和装置。 该方法包括产生响应于模式信号的高电压发生器的使能信号，例如晶片老化测试模式。 该方法通过响应于使能信号的焊盘向半导体存储器件提供外部电压。 该方法响应于参考电压电平而改变从高电压发生器输出的高电压电平。