公开(公告)号：US20100036641A1

公开(公告)日：2010-02-11

申请号：US12318043

申请日：2008-12-19

Applicant: Seung Won Lee ,  Min Soo Ryu ,  Byung Kwan Jung

Inventor： Seung Won Lee ,  Min Soo Ryu ,  Byung Kwan Jung

IPC: G06F15/00

CPC classification number: G06F11/3419 ,  G06F11/3447 ,  G06F2201/86 ,  G06F2201/865

Abstract: A method and system of estimating multi-tasking performance performed in multi-processor are described. The method includes dividing a plurality of tasks into a plurality of sub tasks in accordance with predefined operation types, arranging the plurality of sub tasks in accordance with a predecessor-successor structure based on the operation types of the plurality of sub tasks, and estimating multi-tasking performance of the plurality of tasks using the arranged plurality of sub tasks.

Abstract translation: 描述了在多处理器中执行多任务处理性能的方法和系统。 该方法包括根据预定义的操作类型将多个任务划分为多个子任务，基于多个子任务的操作类型根据前导后继结构排列多个子任务，并且估计多个 使用所排列的多个子任务来分析多个任务的性能。

公开(公告)号：US20080282229A1

公开(公告)日：2008-11-13

申请号：US11984105

申请日：2007-11-13

Applicant: Han-cheol Kim ,  Keun-soo Yim ,  Seung-won Lee ,  Jeong-joon Yoo ,  Jae-don Lee ,  Young-sam Shin

Inventor： Han-cheol Kim ,  Keun-soo Yim ,  Seung-won Lee ,  Jeong-joon Yoo ,  Jae-don Lee ,  Young-sam Shin

IPC: G06F9/44

CPC classification number: G06F11/3648 ,  G06F9/454

Abstract: A method and apparatus for detecting errors in an application software of an embedded system are provided. The method of detecting errors in an application software includes determining a development language of the application software and an operating system on which the application software is executed; replacing an error detection syntax inserted in order to examine an error in a predetermined function of the application software, with an error detection syntax according to the result of the determination; and performing exception handling for an error occurring in the function according to the result of the replacement, and logging error information according to the exception handling. According to the method and apparatus, an error can be automatically detected and logged irrespective of a development language and an operating system.

Abstract translation: 提供一种用于检测嵌入式系统的应用软件中的错误的方法和装置。 检测应用软件中的错误的方法包括确定应用软件的开发语言和执行应用软件的操作系统; 替换插入的错误检测语法，以便根据确定结果具有错误检测语法来检查应用软件的预定功能中的错误; 并且根据替换的结果对功能中发生的错误执行异常处理，并根据异常处理记录错误信息。 根据该方法和装置，无论开发语言和操作系统如何，都可以自动检测和记录错误。

公开(公告)号：US20080195893A1

公开(公告)日：2008-08-14

申请号：US11845194

申请日：2007-08-27

Applicant: Byeong Hoon LEE ,  Ki Hong KIM ,  Seung Won LEE ,  Sun Kwon KIM

Inventor： Byeong Hoon LEE ,  Ki Hong KIM ,  Seung Won LEE ,  Sun Kwon KIM

IPC: G06F11/00

CPC classification number: G06F11/1417 ,  G11C29/82

Abstract: A repairable semiconductor memory device including a memory cell array having a first block to store first system data and a second block to store second system data identical to the first system data. A controller transmits the first system data to a memory unit in response to a reset signal output from a host and the second system data to the memory unit based on a fail detection signal generated by an ECC detection block. The ECC detection block determines whether the first system data is defective. When a defect is generated in the first system data during resetting of the semiconductor memory device, the first system data is repaired by supplying the second system data.

Abstract translation: 一种可修复半导体存储器件，包括具有存储第一系统数据的第一块的存储单元阵列和用于存储与第一系统数据相同的第二系统数据的第二块。 控制器响应于从主机输出的复位信号将第一系统数据发送到存储器单元，并且基于由ECC检测块产生的故障检测信号将第二系统数据传送到存储器单元。 ECC检测块确定第一系统数据是否有缺陷。 当在半导体存储器件复位期间在第一系统数据中产生缺陷时，通过提供第二系统数据来修复第一系统数据。

公开(公告)号：US20080184086A1

公开(公告)日：2008-07-31

申请号：US11830461

申请日：2007-07-30

Applicant: Sun Kwon Kim ,  Byeong Hoon Lee ,  Ki Hong Kim ,  Seung Won Lee

Inventor： Sun Kwon Kim ,  Byeong Hoon Lee ,  Ki Hong Kim ,  Seung Won Lee

IPC: G06F11/07

CPC classification number: G06F11/0793 ,  G06F11/073 ,  G06F11/1068

Abstract: A buffer memory includes a memory cell array, a flag cell array, and a error correction block. The memory cell array has a plurality of word lines. Each of the plurality of word lines are electrically connected to a plurality of memory cells storing data. The flag cell array has a plurality of flag cells. Each of the plurality of flag cells is connected to each of the word lines and stores information that indicates whether error correction of the data has been performed. The error correction block performs error correction on the data output from the memory cell array in response to a command received through a host interface and flag data output from the flag cell array.

Abstract translation: 缓冲存储器包括存储单元阵列，标志单元阵列和纠错块。 存储单元阵列具有多个字线。 多个字线中的每一个电连接到存储数据的多个存储单元。 标志单元阵列具有多个标志单元。 多个标志单元中的每一个连接到每个字线，并且存储指示是否已经执行了数据的纠错的信息。 误差校正块响应于通过主机接口接收的命令和从标志单元阵列输出的标志数据对从存储器单元阵列输出的数据执行纠错。

公开(公告)号：US20080165770A1

公开(公告)日：2008-07-10

申请号：US11979737

申请日：2007-11-07

Applicant: Young-sam Shin ,  Seung-won Lee ,  Han-cheol Kim ,  Jeong-joon Yoo ,  Jae-don Lee ,  Min-kyu Jeong ,  Keun-soo Yim

Inventor： Young-sam Shin ,  Seung-won Lee ,  Han-cheol Kim ,  Jeong-joon Yoo ,  Jae-don Lee ,  Min-kyu Jeong ,  Keun-soo Yim

IPC: H04L12/56

CPC classification number: H04L47/564 ,  H04L47/19 ,  H04L47/24 ,  H04L47/50

Abstract: A method and apparatus transmitting and receiving in a real-time system are disclosed. The method of transmitting in a real-time system includes scheduling a task included in a socket based on a predetermined transmission option designated to the socket, and transmitting a packet generated by the scheduled task based on the predetermined transmission option, so that real-time communications of a network communication can be secured and resources of the system can be efficiently used, thereby, transmitting and receiving data according to the required characteristics of transmission and reception.

Abstract translation: 公开了一种在实时系统中发送和接收的方法和装置。 在实时系统中发送的方法包括基于指定给套接字的预定传输选项来调度包含在套接字中的任务，以及基于预定传输选项发送由调度任务生成的分组，使得实时 可以确保网络通信的通信，并且可以有效地利用系统的资源，从而根据所需的发送和接收特性发送和接收数据。

公开(公告)号：US20080143312A1

公开(公告)日：2008-06-19

申请号：US11951594

申请日：2007-12-06

Applicant: Seung-Won Lee

Inventor： Seung-Won Lee

IPC: G05F1/00

CPC classification number: G05F1/56

Abstract: A voltage controller may include a pulse generator and an internal voltage control circuit coupled to the pulse generator. The pulse generator may be configured to generate a control signal in response to at least one of a mode signal and/or an external voltage. The internal voltage control circuit may be configured to generate an internal voltage at an internal voltage node, and the internal voltage control circuit may include a voltage divider, first and second comparators, and a driver. The voltage divider may be coupled between the internal voltage node and a first reference voltage, and the voltage divider may generate a feedback voltage that is between the internal voltage and the first reference voltage. The first comparator may be configured to generate a first comparison result responsive to comparing the feedback voltage with a second reference voltage, and the second comparator may be configured to generate a second comparison result responsive to comparing the feedback voltage with the second reference voltage in response to the control signal. The driver may be coupled between an external voltage and the internal voltage node, and the driver may be configured to generate the internal voltage responsive to the first and second comparison results. Related methods and smart cards are also discussed.

Abstract translation: 电压控制器可以包括脉冲发生器和耦合到脉冲发生器的内部电压控制电路。 脉冲发生器可以被配置为响应于模式信号和/或外部电压中的至少一个而产生控制信号。 内部电压控制电路可以被配置为在内部电压节点处产生内部电压，并且内部电压控制电路可以包括分压器，第一和第二比较器以及驱动器。 分压器可以耦合在内部电压节点和第一参考电压之间，并且分压器可以产生处于内部电压和第一参考电压之间的反馈电压。 第一比较器可以被配置为响应于将反馈电压与第二参考电压进行比较而产生第一比较结果，并且第二比较器可以被配置为响应于响应于将反馈电压与响应于第二参考电压进行比较而产生第二比较结果 到控制信号。 驱动器可以耦合在外部电压和内部电压节点之间，并且驱动器可以被配置为响应于第一和第二比较结果而产生内部电压。 还讨论了相关方法和智能卡。

公开(公告)号：US20070183205A1

公开(公告)日：2007-08-09

申请号：US11652823

申请日：2007-01-12

Applicant: Seung-Won Lee

Inventor： Seung-Won Lee

IPC: G11C16/04

CPC classification number: H01L29/7881 ,  G11C16/30

Abstract: A semiconductor memory device controlling a program voltage according to the number of cells to be programmed and a method of programming the same. The semiconductor memory device includes a memory cell array. A write data buffer receives write data in a predetermined unit. A program cell counter calculates the amount of data, from the write data, to be programmed in the memory cell array. A program voltage generator outputs a program voltage to be applied to the memory cell array, in accordance with the amount of data to be programmed, at a time, in the memory cell array. The program voltage is controlled in accordance with the number of memory cells to be programmed.

Abstract translation: 根据要编程的单元数量控制编程电压的半导体存储器件及其编程方法。 半导体存储器件包括存储单元阵列。 写数据缓冲器以预定单元接收写数据。 程序单元计数器从写入数据计算要在存储器单元阵列中编程的数据量。 程序电压发生器根据存储单元阵列中每次要编程的数据量来输出要施加到存储单元阵列的编程电压。 程序电压根据要编程的存储单元的数量进行控制。

公开(公告)号：US20070080453A1

公开(公告)日：2007-04-12

申请号：US11542283

申请日：2006-10-03

Applicant: Woo-jin Jang ,  Seung-won Lee

Inventor： Woo-jin Jang ,  Seung-won Lee

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/05666 ,  H01L2224/13099 ,  H01L2224/13166 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/01074 ,  H01L2224/05599

Abstract: A semiconductor chip includes a plurality of chip pads and a plurality of bumps formed on respective chip pads, each bumps including a bump main body and a conductive particle disposed on the bump main body and exposed to the air, the conductive particle including an elastic portion made of an elastic material and a conductive layer enclosing the elastic portion.

Abstract translation: 半导体芯片包括多个芯片焊盘和形成在各个芯片焊盘上的多个凸块，每个凸块包括设置在凸块主体上并暴露于空气的凸块主体和导电颗粒，导电颗粒包括弹性部分 由弹性材料制成，导电层由弹性部分包围。

公开(公告)号：US20070041425A1

公开(公告)日：2007-02-22

申请号：US11452781

申请日：2006-06-14

Applicant: Seung-won Lee ,  Eui-seung Kim

Inventor： Seung-won Lee ,  Eui-seung Kim

IPC: G01K1/00

CPC classification number: G01K15/00

Abstract: A temperature detector, a temperature detecting method, and a semiconductor device having the temperature detector, in which the temperature detector includes a voltage generator, a selection circuit, and a comparator. The voltage generator generates first and second voltages that are inversely proportional to temperature. The selection circuit outputs the first voltage during a normal operation, and the second voltage during a self-test operation, wherein the second voltage is lower than the first voltage. The comparator compares a reference voltage with one of the first and second voltages output from the selection circuit, and generates a detection signal according to the comparison result. The temperature detecting method is performed by the temperature detector. The semiconductor device includes a reset signal generator that generates a reset signal for resetting a central processing unit (CPU) in response to a detection signal output from the temperature detector.

Abstract translation: 温度检测器，温度检测方法和具有温度检测器的半导体器件，其中温度检测器包括电压发生器，选择电路和比较器。 电压发生器产生与温度成反比的第一和第二电压。 选择电路在正常操作期间输出第一电压，在自检操作期间输出第二电压，其中第二电压低于第一电压。 比较器将参考电压与从选择电路输出的第一和第二电压之一进行比较，并根据比较结果生成检测信号。 温度检测方法由温度检测器进行。 半导体器件包括复位信号发生器，其响应于从温度检测器输出的检测信号而产生用于复位中央处理单元（CPU）的复位信号。

公开(公告)号：US07142457B2

公开(公告)日：2006-11-28

申请号：US11327045

申请日：2006-01-06

Applicant: Seung-Won Lee ,  Seung-Keun Lee

Inventor： Seung-Won Lee ,  Seung-Keun Lee

IPC: G11C16/26

CPC classification number: G11C7/062 ,  G11C7/18 ,  G11C16/04 ,  G11C16/28 ,  G11C29/24 ,  G11C29/50004

Abstract: A memory device in accordance with embodiments of the present invention includes a reference cell array and a plurality of banks. Each of the banks includes memory cells. A plurality of current copier circuits corresponds to the banks, respectively. Each of the current copier circuits copies a reference current flowing through a reference cell array to generate a reference voltage. A plurality of sense blocks correspond to the banks, respectively. Each of the sense blocks includes a plurality of sense amplifiers for sensing data from a corresponding bank in response to the reference voltage from the corresponding current copier circuit. Memory cell lay-out area is reduced, and sense speed is increased.