公开(公告)号：US06428398B2

公开(公告)日：2002-08-06

申请号：US09737738

申请日：2000-12-18

Applicant: Shin Hashimoto ,  Yoshiharu Hidaka

Inventor： Shin Hashimoto ,  Yoshiharu Hidaka

IPC: B24B100

CPC classification number: B24B53/017 ,  B24B37/042 ,  H01L21/02024 ,  H01L21/30625

Abstract: It is arranged such that the least common multiple of two numbers m and n of which one is prime to the other, is made as large as possible where the number m is the rotational speed (rpm) of a platen with a polishing pad affixed thereto and the number n is the rotational speed (rpm) of a carrier with a wafer mounted thereon. As a result of such arrangement, it is not until the platen completes m revolutions that a point on the polishing pad that comes into contact with a fixed point on the wafer returns to the original contact point with the fixed point at the start of polishing, and the resulting trajectory is therefore spread uniformly over the polishing pad. Each point on the wafer is brought into contact with most surface regions of the polishing pad, therefore preventing the wafer from undergoing deterioration in planarity uniformity due to a particular point on the wafer, on one hand, frequently coming into contact with low polishing-rate regions in the polishing pad and due to the other points on the wafer, on the other hand, less frequently coming into contact with the regions.

Abstract translation: 它被布置为使得其中一个是另一个的两个数m和n的最小公倍数被制成尽可能大，其中数字m是固定有抛光垫的压板的转速（rpm） 数字n是安装有晶片的载体的转速（rpm）。 作为这种布置的结果，直到压板完成m转，即抛光垫上的与晶片上的固定点接触的点在抛光开始时返回到与固定点的原始接触点， 并且所得到的轨迹因此均匀地分布在抛光垫上。 晶片上的每个点与抛光垫的大多数表面区域接触，因此防止晶片由于晶片上的特定点而在平坦度均匀性方面的劣化，一方面经常与低抛光速率接触 另一方面，抛光垫中的区域和晶片上的其它点，较不频繁地与该区域接触。

公开(公告)号：US06319099B1

公开(公告)日：2001-11-20

申请号：US09447573

申请日：1999-11-23

Applicant: Akihiro Tanoue ,  Yoshiharu Hidaka ,  Shin Hashimoto

Inventor： Akihiro Tanoue ,  Yoshiharu Hidaka ,  Shin Hashimoto

IPC: B24B100

CPC classification number: B24B37/04 ,  B24B57/02

Abstract: A slurry feeding apparatus includes closed slurry bottle, piping, wet nitrogen generator, wet nitrogen supply pipe, suction and spray nozzles, temperature regulator, flow rate control valves, slurry delivery pump and controller for controlling the operation and flow rate of the slurry delivery pump. While a wafer is being polished by a CMP polisher, the controller continuously operates the pump. On the other hand, while the polisher is idling, the controller starts and stops the pump intermittently at regular intervals. No stirrer like a propeller is inserted into the slurry bottle, but the slurry is stirred up by spraying the slurry through the spray nozzle.

Abstract translation: 浆料输送装置包括封闭的浆液瓶，管道，湿氮发生器，湿氮供给管，抽吸喷嘴，温度调节器，流量控制阀，浆料输送泵和用于控制浆料输送泵的操作和流速的控制器 。 当晶圆被CMP抛光机抛光时，控制器连续地操作泵。 另一方面，当抛光机空转时，控制器会间歇地间歇地启动和停止泵。 没有像螺旋桨那样的搅拌器被插入到浆料瓶中，但是通过喷雾喷雾浆料来搅拌浆料。

公开(公告)号：US5945834A

公开(公告)日：1999-08-31

申请号：US609150

申请日：1996-02-29

Applicant: Yoshirou Nakata ,  Toshio Yamada ,  Atsushi Fujiwara ,  Isao Miyanaga ,  Shin Hashimoto ,  Yukiharu Uraoka ,  Yasushi Okuda ,  Kenzou Hatada

Inventor： Yoshirou Nakata ,  Toshio Yamada ,  Atsushi Fujiwara ,  Isao Miyanaga ,  Shin Hashimoto ,  Yukiharu Uraoka ,  Yasushi Okuda ,  Kenzou Hatada

IPC: G01R1/04 ,  G01R1/073 ,  G01R31/28 ,  H01L21/66

CPC classification number: G01R31/2886 ,  G01R1/0491 ,  G01R31/2867 ,  G01R31/2831

Abstract: A retainer board, holding a semiconductor wafer having a plurality of integrated circuit terminals for testing a semiconductor chip, is provided in confronting relation to a probe sheet having a plurality of probe terminals electrically connected to their corresponding integrated circuit terminals. An insulating substrate, having wiring electrically connected to the plural probe terminals, is provided on the probe sheet in opposed relation to the retainer board. An elastic member is interposed between the probe sheet and the insulating substrate. The retainer board and the probe sheet are brought into so closer relationship that each integrated circuit terminal of the semiconductor wafer held by the retainer board is electrically connected to its corresponding probe terminal of the probe sheet.

公开(公告)号：US5405800A

公开(公告)日：1995-04-11

申请号：US274048

申请日：1994-07-12

Applicant: Hisashi Ogawa ,  Susumu Matsumoto ,  Shin Hashimoto ,  Hiroyuki Umimoto

Inventor： Hisashi Ogawa ,  Susumu Matsumoto ,  Shin Hashimoto ,  Hiroyuki Umimoto

IPC: H01L27/108 ,  H01L21/70

CPC classification number: H01L27/10808

Abstract: A method of fabricating a semiconductor memory device on a semiconductor substrate is disclosed. A gate electrode that becomes a word line, a bit line, and a charge-storage electrode are formed in a memory cell array region of a semiconductor substrate. A capacitor insulator layer and a plate electrode are formed in that order. Then, a BPSG film is formed in the memory cell array region and in the peripheral circuit region. A resist pattern is formed on the BPSG film, leaving the memory cell array region exposed. Using the resist pattern thus formed as a mask, an etching treatment is applied to remove an upper surface portion of the BPSG film lying within the memory cell array region by a given amount. After the resist pattern is removed, the BPSG film is heated in order that it reflows to planarize.

Abstract translation: 公开了一种在半导体衬底上制造半导体存储器件的方法。 在半导体衬底的存储单元阵列区域中形成成为字线，位线和电荷存储电极的栅电极。 依次形成电容器绝缘体层和平板电极。 然后，在存储单元阵列区域和外围电路区域中形成BPSG膜。 在BPSG膜上形成抗蚀剂图案，使存储单元阵列区域暴露。 使用如此形成的抗蚀剂图案作为掩模，进行蚀刻处理以将存在于存储单元阵列区域内的BPSG膜的上表面部分除去给定量。 在除去抗蚀剂图案之后，加热BPSG膜，使其回流平坦化。