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    Policies for shader resource allocation in a shader core
    71.
    发明授权
    Policies for shader resource allocation in a shader core 有权

    公开(公告)号：US10579388B2

    公开(公告)日：2020-03-03

    申请号：US16040224

    申请日：2018-07-19

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Robert Scott Hartog ,  Mark Leather ,  Michael Mantor ,  Rex McCrary ,  Sebastien Nussbaum ,  Philip J. Rogers ,  Ralph Clay Taylor ,  Thomas Woller

    IPC: G06F9/38 ,  G06F9/48 ,  G06T1/20

    Abstract: A method for use in a processor for arbitrating between multiple processes to select wavefronts for execution on a shader core is provided. The processor includes a compute pipeline configured to issue wavefronts to the shader core for execution, a hardware queue descriptor associated with the compute pipeline, and the shader core. The shader core is configured to execute work for the compute pipeline corresponding to a first memory queue descriptor executed using data for the first memory queue descriptor that is loaded into a first hardware queue descriptor. The processor is configured to detect a context switch condition, and, responsive to the context switch condition, perform a context switch operation including loading data for a second memory queue descriptor into the first hardware queue descriptor. The shader core is configured to execute work corresponding to the second memory queue descriptor that is loaded into the first hardware queue descriptor.

    Split frame rendering
    72.
    发明授权
    Split frame rendering 有权

    公开(公告)号：US10388056B2

    公开(公告)日：2019-08-20

    申请号：US15417063

    申请日：2017-01-26

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Mangesh P. Nijasure ,  Todd Martin ,  Michael Mantor

    IPC: G06T15/00 ,  G06T11/40 ,  G06F9/44

    Abstract: Improvements in the graphics processing pipeline that allow multiple pipelines to cooperate to render a single frame are disclosed. Two approaches are provided. In a first approach, world-space pipelines for the different graphics processing pipelines process all work for draw calls received from a central processing unit (CPU). In a second approach, the world-space pipelines divide up the work. Work that is divided is synchronized and redistributed at various points in the world-space pipeline. In either approach, the triangles output by the world-space pipelines are distributed to the screen-space pipelines based on the portions of the render surface overlapped by the triangles. Triangles are rendered by screen-space pipelines associated with the render surface portions overlapped by those triangles.

    Primitive level preemption using discrete non-real-time and real time pipelines
    76.
    发明授权
    Primitive level preemption using discrete non-real-time and real time pipelines 有权

    公开(公告)号：US10210650B1

    公开(公告)日：2019-02-19

    申请号：US15828055

    申请日：2017-11-30

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Anirudh R. Acharya ,  Swapnil Sakharshete ,  Michael Mantor ,  Mangesh P. Nijasure ,  Todd Martin ,  Vineet Goel

    IPC: G06T15/00 ,  G06T1/20 ,  G06T15/80 ,  G06F9/48 ,  G06F9/50

    Abstract: Processing of non-real-time and real-time workloads is performed using discrete pipelines. A first pipeline includes a first shader and one or more fixed function hardware blocks. A second pipeline includes a second shader that is configured to emulate the at least one fixed function hardware block. First and second memory elements store first state information for the first pipeline and second state information for the second pipeline, respectively. A non-real-time workload executing in the first pipeline is preempted at a primitive boundary in response to a real-time workload being dispatched for execution in the second pipeline. The first memory element retains the first state information in response to preemption of the non-real-time workload. The first pipeline is configured to resume processing the subsequent primitive on the basis of the first state information stored in the first memory element.

    Method and System for Synchronization of Workitems with Divergent Control Flow
    77.
    发明申请
    Method and System for Synchronization of Workitems with Divergent Control Flow 有权
    工作单元与发散控制流程同步的方法与系统

    公开(公告)号：US20130326524A1

    公开(公告)日：2013-12-05

    申请号：US13672291

    申请日：2012-11-08

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Michael C. HOUSTON ,  Benedict R. Gaster ,  Lee W. Howes ,  Michael Mantor ,  Dominik Behr

    IPC: G06F9/52

    CPC classification number: G06F9/52 ,  G06F9/522

    Abstract: Disclosed methods, systems, and computer program products embodiments include synchronizing a group of workitems on a processor by storing a respective program counter associated with each of the workitems, selecting at least one first workitem from the group for execution, and executing the selected at least one first workitem on the processor. The selecting is based upon the respective stored program counter associated with the at least one first workitem.

    Abstract translation: 公开的方法，系统和计算机程序产品实施例包括通过存储与每个工作项相关联的相应程序计数器来同步处理器上的一组工作项，从组中选择至少一个第一工作以供执行，以及执行所选择的至少 处理器上的第一个工作。 所述选择基于与所述至少一个第一工作项相关联的相应存储的程序计数器。

    Dual vector arithmetic logic unit
    78.
    发明授权
    Dual vector arithmetic logic unit 有权

    公开(公告)号：US12299413B2

    公开(公告)日：2025-05-13

    申请号：US18414164

    申请日：2024-01-16

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Bin He ,  Brian Emberling ,  Mark Leather ,  Michael Mantor

    IPC: G06F7/57 ,  G06F9/38 ,  G06F17/16 ,  G06T1/20 ,  G06F15/80

    Abstract: A processing system executes wavefronts at multiple arithmetic logic unit (ALU) pipelines of a single instruction multiple data (SIMD) unit in a single execution cycle. The ALU pipelines each include a number of ALUs that execute instructions on wavefront operands that are collected from vector general process register (VGPR) banks at a cache and output results of the instructions executed on the wavefronts at a buffer. By storing wavefronts supplied by the VGPR banks at the cache, a greater number of wavefronts can be made available to the SIMD unit without increasing the VGPR bandwidth, enabling multiple ALU pipelines to execute instructions during a single execution cycle.

    Reconfigurable virtual graphics and compute processor pipeline
    80.
    发明授权
    Reconfigurable virtual graphics and compute processor pipeline 有权

    公开(公告)号：US12254527B2

    公开(公告)日：2025-03-18

    申请号：US16879991

    申请日：2020-05-21

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Timour T. Paltashev ,  Michael Mantor ,  Rex Eldon McCrary

    IPC: G06T1/20 ,  G06T1/60 ,  G06T15/00 ,  G06T15/80 ,  G06T17/10

    Abstract: A graphics processing unit (GPU) includes a plurality of programmable processing cores configured to process graphics primitives and corresponding data and a plurality of fixed-function hardware units. The plurality of processing cores and the plurality of fixed-function hardware units are configured to implement a configurable number of virtual pipelines to concurrently process different command flows. Each virtual pipeline includes a configurable number of fragments and an operational state of each virtual pipeline is specified by a different context. The configurable number of virtual pipelines can be modified from a first number to a second number that is different than the first number. An emulation of a fixed-function hardware unit can be instantiated on one or more of the graphics processing cores in response to detection of a bottleneck in a fixed-function hardware unit. One or more of the virtual pipelines can then be reconfigured to utilize the emulation instead of the fixed-function hardware unit.

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