公开(公告)号：US06804311B1

公开(公告)日：2004-10-12

申请号：US09526019

申请日：2000-03-15

申请人： Anand G. Dabak ,  Srinath Hosur ,  Shigenori Kinjo ,  Alan Gatherer

发明人： Anand G. Dabak ,  Srinath Hosur ,  Shigenori Kinjo ,  Alan Gatherer

IPC分类号： H04L2720

CPC分类号： H04B7/06 ,  H04L25/0228

摘要： A circuit for detecting a transmit diversity signal comprises a first circuit (706) arranged to receive a first synchronization code. The first synchronization code is modulated by a data signal. The first circuit produces a first output signal. A second circuit (732) is arranged to receive a plurality of predetermined signals. The second circuit produces a channel estimate. A detection circuit (710, 712) is arranged to receive the first output signal and the channel estimate. The detection circuit produces a signal corresponding to the data signal.

摘要翻译： 用于检测发射分集信号的电路包括布置成接收第一同步码的第一电路（706）。 第一同步码由数据信号调制。 第一电路产生第一输出信号。 第二电路（732）被布置成接收多个预定信号。 第二电路产生信道估计。 检测电路（710,712）被布置成接收第一输出信号和信道估计。 检测电路产生对应于数据信号的信号。

公开(公告)号：US06725025B1

公开(公告)日：2004-04-20

申请号：US09665843

申请日：2000-09-20

申请人： Timothy M. Schmidl ,  Alan Gatherer ,  Xiaodong Wang ,  Rong Chen

发明人： Timothy M. Schmidl ,  Alan Gatherer ,  Xiaodong Wang ,  Rong Chen

IPC分类号： H04B106

CPC分类号： H04B1/71075 ,  H04L25/067

摘要： An improved interference cancellation technique is disclosed. Digital baseband circuitry (40) includes user and symbol detection circuitry (50) for performing a Gibbs sampler type of interference cancellation, either embodied in custom hardware (44) or in software. Random initial guesses for a signal sample (either a symbol or chip) are made for each user. Interference cancellation is performed on a user-by-user basis, using the then-current data decision values for the other, interfering users. A soft data decision is used to derive a probability distribution function for the actual data decision for the sample for the user. A randomly selected value is applied against the probability distribution function to generate the next data decision value for that user, and the process is repeated until convergence. Following convergence, a statistic is used to select a final data decision value for each user, from the set of intermediate data decision values stored in memory.

摘要翻译： 公开了一种改进的干扰消除技术。 数字基带电路（40）包括用于执行Gibbs采样器类型的干扰消除的用户和符号检测电路（50），或者体现在定制硬件（44）中或软件中。 为每个用户制作信号样本（符号或芯片）的随机初始猜测。 干扰消除是在逐个用户的基础上，使用当时的其他干扰用户的当前数据判定值进行的。 软数据决策用于导出用于用户的样本的实际数据决定的概率分布函数。 对概率分布函数应用随机选择的值以生成该用户的下一个数据判定值，并重复该过程直到收敛。 收敛后，根据存储在存储器中的一组中间数据判定值，使用统计量为每个用户选择最终数据判定值。

公开(公告)号：US06480534B1

公开(公告)日：2002-11-12

申请号：US09165450

申请日：1998-10-02

申请人： Alan Gatherer ,  Hiep Van Tran

发明人： Alan Gatherer ,  Hiep Van Tran

IPC分类号： H03H730

CPC分类号： H03H21/0012 ,  H04L25/03038 ,  H04L2025/03477

摘要： In an equalizer filter unit, the filter is divided into a plurality of sequential segments. While all the components of the equalizer unit multiply data signal groups by the a coefficient signal group, in only one segment are the coefficient signal groups updated. The data and the coefficient signal groups are periodically transferred to the next sequential filter segment while the filter segments are reconfigured in the original sequential order. In this manner, the each data signal group interacts with a coefficient signal group in the original sequential order. Because the coefficients are updated in only one of the filter segments, the amount of apparatus required for processing signal groups is reduced.

摘要翻译： 在均衡器滤波器单元中，滤波器被分成多个顺序段。 虽然均衡器单元的所有组件都将数据信号组乘以系数信号组，但是在仅一个段中更新了系数信号组。 将数据和系数信号组周期性地传送到下一个顺序滤波器段，同时以原始顺序重新配置滤波器段。 以这种方式，每个数据信号组以原始顺序与系数信号组进行交互。 因为仅在一个滤波器段中更新系数，所以减少了处理信号组所需的装置量。

公开(公告)号：US06421355B1

公开(公告)日：2002-07-16

申请号：US09107065

申请日：1998-06-29

申请人： Keith L. Quiring ,  Alan Gatherer ,  Ray A. King

发明人： Keith L. Quiring ,  Alan Gatherer ,  Ray A. King

IPC分类号： H04J316

CPC分类号： H04J3/1682 ,  G06F13/409

摘要： A linecard codec (250) permitting an increased throughput connection between a subscriber modem (20) and a service provider coupled to a digital backplane (150). The linecard codec (250) includes an analog interface (152) to the Public Switched Telephone Network, a digital interface (119) to the digital backplane (150), conversion circuits (258, 280) interspersed between the analog interface (152) and the digital interface (119), and a controller (340) having a network interface (350) and configured to format requests for bandwidth and transmit them to a network administrator of the digital backplane (150). A code recognition mechanism (272) is used to monitor the Pulse Code Modulated (PCM) signals from service providers and in combination with control logic (300) and the controller (340) provides a way to allocate and deallocate timeslots on the digital backplane (150).

摘要翻译： 线卡解码器（250）允许在用户调制解调器（20）和耦合到数字背板（150）的服务提供商之间增加吞吐量连接。 线路编解码器（250）包括到公共交换电话网络的模拟接口（152），数字背板（150）的数字接口（119），散布在模拟接口（152）和 数字接口（119）和具有网络接口（350）并被配置为格式化带宽请求并将其发送到数字背板（150）的网络管理员的控制器（340）。 代码识别机制（272）用于监视来自服务提供商的脉码调制（PCM）信号，并结合控制逻辑（300），并且控制器（340）提供分配和释放数字背板上的时隙 150）。

公开(公告)号：US06275548B1

公开(公告)日：2001-08-14

申请号：US09243763

申请日：1999-02-03

申请人： Tod D. Wolf ,  Alan Gatherer

发明人： Tod D. Wolf ,  Alan Gatherer

IPC分类号： H04L700

CPC分类号： H04L27/38 ,  H04L7/0278

摘要： The preferred embodiments generalize the Band Edge Component Maximization (BECM) timing recovery method and provide blind timing recovery in Quadrature Amplitude Modulation (QAM) using all the available information rather than sampling the BECM output at the symbol rate.

摘要翻译： 优选实施例概括了带边缘组件最大化（BECM）定时恢复方法，并且使用所有可用信息提供正交幅度调制（QAM）中的盲定时恢复，而不是以符号速率采样BECM输出。

公开(公告)号：US06256724B1

公开(公告)日：2001-07-03

申请号：US09244674

申请日：1999-02-04

申请人： Dale E. Hocevar ,  Alan Gatherer ,  Carl E. Lemonds, Jr. ,  Ching-Yu Hung

发明人： Dale E. Hocevar ,  Alan Gatherer ,  Carl E. Lemonds, Jr. ,  Ching-Yu Hung

IPC分类号： G06F1316

CPC分类号： G06F9/3879 ,  G06F9/3897

摘要： A data processing system includes a digital signal processor core and a co-processor. The co-processor has a local memory within the address space of the said digital signal processor core. The co-processor responds commands from the digital signal processor core. A direct memory access circuit autonomously transfers data to and from the local memory of the co-processor. Co-processor commands are stored in a command FIFO memory mapped to a predetermined memory address. Control commands includes a receive data synchronism command stalling the co-processor until completion of a memory transfer into the local memory. A send data synchronism command causes the co-processor to signal the direct memory access circuit to trigger memory transfer out of the local memory. An interrupt command causes the co-processor to interrupt the digital signal processor core.

摘要翻译： 数据处理系统包括数字信号处理器核和协处理器。 协处理器在所述数字信号处理器核心的地址空间内具有本地存储器。 协处理器响应来自数字信号处理器核心的命令。 直接存储器访问电路自主地将数据传送到协处理器的本地存储器和/或从协处理器的本地存储器传送数据。 协处理器命令存储在映射到预定存储器地址的命令FIFO存储器中。 控制命令包括停止协处理器的接收数据同步命令，直到完成到本地存储器的存储器传送。 发送数据同步命令使协处理器向直接存储器访问电路发出信号，以触发从本地存储器传出的存储器。 中断命令使协处理器中断数字信号处理器内核。

公开(公告)号：US6058404A

公开(公告)日：2000-05-02

申请号：US838841

申请日：1997-04-11

申请人： Shivaling Mahant-Shetti ,  Alan Gatherer

发明人： Shivaling Mahant-Shetti ,  Alan Gatherer

IPC分类号： H03H17/02 ,  G06F17/10

CPC分类号： H03H17/02

摘要： A digital filter can be implemented with a reduced number of components for a transform function having specific characteristics in the regions outside of a center region. The characteristics are that the transform function waveform is periodic with period T and has or can be approximated by at least one envelope, the envelope decaying a multiplier constant for each period T in a direction away from the waveform center. The digital filter has three groups of elements. A center group of components functions in a manner similar to the prior digital filters. A positive time group of components receives the signals from the center, and using a group of delay component, delays the signal by one period T, is reduced by the multiplier constant factor, and after having the current signal from the center group applied thereto, is once again applied to the positive time group delay components. Each positive time group delay component has coefficient multiplier component which multiplies the signal in the associated delay component by a cumulative coefficient prior to applying the signal to the output line. The negative time group of components can include a group of delay components and coefficient multiplier components which function in the prior art manner. In the alternative, the negative time group of components can include a series of delay component which applies the signal transmitted therethrough to the center group of components and to the a negative time group of component similar in structure and function to the positive time group of components.

摘要翻译： 可以在中心区域外的区域中具有特定特征的变换函数的数量减少的部件来实现数字滤波器。 特征是变换函数波形与周期T是周期性的，并且具有或可以由至少一个包络近似，该包络在远离波形中心的方向上衰减每个周期T的乘数常数。 数字滤波器有三组元件。 中心组件的组件以类似于先前的数字滤波器的方式起作用。 正时间分组接收来自中心的信号，并且使用一组延迟分量将信号延迟一个周期T，减小乘数常数因子，并且在将来自中心组的当前信号应用于其之后， 再次应用于正时间组延迟组件。 每个正时间组延迟分量具有系数乘法器分量，其在将信号施加到输出线之前将相关延迟分量中的信号乘以累积系数。 组件的负时间组可以包括以现有技术方式起作用的一组延迟分量和系数乘数分量。 在替代方案中，组件的负时间组可以包括一系列延迟分量，其将通过其传输的信号施加到组分的中心组，并且将结构和功能相似的组件的负时间组与组件的正时间组 。

公开(公告)号：US6044107A

公开(公告)日：2000-03-28

申请号：US748444

申请日：1996-11-13

申请人： Alan Gatherer ,  Mohammed Nafie ,  Donald P. Shaver

发明人： Alan Gatherer ,  Mohammed Nafie ,  Donald P. Shaver

IPC分类号： H04L1/00 ,  H04L1/16 ,  H04L5/14 ,  H04L25/03 ,  H04L25/49 ,  H04L27/00 ,  H04L27/26 ,  H04M11/06 ,  H04B1/38

CPC分类号： H04L27/0008 ,  H04L1/0003 ,  H04L1/0009 ,  H04L1/0016 ,  H04L1/0023 ,  H04L1/0059 ,  H04L25/03 ,  H04L25/03343 ,  H04L25/4921 ,  H04L27/2647 ,  H04L5/1438 ,  H04M11/06 ,  H04M11/062 ,  H04L1/16 ,  H04L2025/03414 ,  H04L2025/03611 ,  H04L27/2649

摘要： An MDSL modem is provided that is inter-operable with an ADSL modem. The present invention provides a method for modem operation, by dividing available bandwidth for the modem into a plurality of subsets, selecting at least one of the plurality of subsets for use as a communication path, reducing the SNR value used for bit loading for the selected subsets by a predetermined amount, undersampling any received data, and fast fourier transforming the received data to recover the data transmitted. An MDSL modem is provided having circuitry for dividing available bandwidth for the modem into a plurality of subsets, circuitry for selecting at least one of the plurality of subsets for use as a communication path, circuitry for reducing the SNR value used for bit loading for the selected subsets by a predetermined amount, circuitry for undersampling any received data, and circuitry for fast fourier transforming the received data to recover the data transmitted.

摘要翻译： 提供与ADSL调制解调器相互操作的MDSL调制解调器。 本发明提供一种用于调制解调器操作的方法，通过将调制解调器的可用带宽划分为多个子集，选择多个子集中的至少一个用作通信路径，减少用于所选择的位加载的SNR值 子集预定量，对任何接收到的数据进行欠采样，并且对接收到的数据进行快速傅立叶变换以恢复发送的数据。 提供了一种MDSL调制解调器，其具有用于将调制解调器的可用带宽分成多个子集的电路，用于选择多个子集中的至少一个用作通信路径的电路，用于减少用于位加载的SNR值的电路 所选择的子集预定量，用于欠采样任何接收数据的电路，以及用于对所接收的数据进行快速傅立叶变换的电路，以恢复发送的数据。

公开(公告)号：US5802461A

公开(公告)日：1998-09-01

申请号：US714645

申请日：1996-09-16

申请人： Alan Gatherer

发明人： Alan Gatherer

IPC分类号： H03J7/04 ,  H04L7/027 ,  H04N21/2383 ,  H04N21/438 ,  H03C1/60 ,  H04B1/68 ,  H04H1/00

CPC分类号： H04L7/027 ,  H03J7/04 ,  H04N21/2383 ,  H04N21/4382

摘要： Apparatus and method (10) for recovering timing information from a vestigial sideband (VSB) modulated signal generate a left hand component signal and a right hand component signal from the received signal, and filters B.sub.1 (f) and B.sub.r (f) (12, 14) filter the left hand and right hand component signals respectively. The filtered signals are then multiplied together without taking the complex conjugate of either signal, as in band edge component maximization (BECM). The generated output signal may be used in a feedback loop to regulate the sample rate of an analog to digital converter (32).

摘要翻译： 用于从残留边带（VSB）调制信号中恢复定时信息的装置和方法（10）从接收信号产生左手分量信号和右手分量信号，滤波器B1（f）和Br（f）（12） 14）分别过滤左手和右手分量信号。 然后将滤波后的信号相乘在一起，而不会取得任一信号的复共轭，如在带边缘分量最大化（BECM）中。 产生的输出信号可以用在反馈回路中以调节模数转换器（32）的采样率。