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公开(公告)号：US6058404A
公开(公告)日：2000-05-02
申请号：US838841
申请日：1997-04-11
CPC分类号： H03H17/02
摘要： A digital filter can be implemented with a reduced number of components for a transform function having specific characteristics in the regions outside of a center region. The characteristics are that the transform function waveform is periodic with period T and has or can be approximated by at least one envelope, the envelope decaying a multiplier constant for each period T in a direction away from the waveform center. The digital filter has three groups of elements. A center group of components functions in a manner similar to the prior digital filters. A positive time group of components receives the signals from the center, and using a group of delay component, delays the signal by one period T, is reduced by the multiplier constant factor, and after having the current signal from the center group applied thereto, is once again applied to the positive time group delay components. Each positive time group delay component has coefficient multiplier component which multiplies the signal in the associated delay component by a cumulative coefficient prior to applying the signal to the output line. The negative time group of components can include a group of delay components and coefficient multiplier components which function in the prior art manner. In the alternative, the negative time group of components can include a series of delay component which applies the signal transmitted therethrough to the center group of components and to the a negative time group of component similar in structure and function to the positive time group of components.
摘要翻译： 可以在中心区域外的区域中具有特定特征的变换函数的数量减少的部件来实现数字滤波器。 特征是变换函数波形与周期T是周期性的，并且具有或可以由至少一个包络近似，该包络在远离波形中心的方向上衰减每个周期T的乘数常数。 数字滤波器有三组元件。 中心组件的组件以类似于先前的数字滤波器的方式起作用。 正时间分组接收来自中心的信号，并且使用一组延迟分量将信号延迟一个周期T，减小乘数常数因子，并且在将来自中心组的当前信号应用于其之后， 再次应用于正时间组延迟组件。 每个正时间组延迟分量具有系数乘法器分量，其在将信号施加到输出线之前将相关延迟分量中的信号乘以累积系数。 组件的负时间组可以包括以现有技术方式起作用的一组延迟分量和系数乘数分量。 在替代方案中，组件的负时间组可以包括一系列延迟分量，其将通过其传输的信号施加到组分的中心组，并且将结构和功能相似的组件的负时间组与组件的正时间组 。
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公开(公告)号：US5612632A
公开(公告)日：1997-03-18
申请号：US346562
申请日：1994-11-29
申请人： Shivaling Mahant-Shetti , Kevin Ovens , Clive Bittlestone , Robert C. Martin , Robert J. Landers
发明人： Shivaling Mahant-Shetti , Kevin Ovens , Clive Bittlestone , Robert C. Martin , Robert J. Landers
IPC分类号： H03K3/037 , H03K3/356 , H03K19/173 , H03K19/00
CPC分类号： H03K3/356173 , H03K3/037 , H03K3/356156
摘要： A flip-flop includes a data storage node for driving an inverter (62) and transfer gate (64) combination to transfer data stored on the data node (60) to a master storage node (66). A master cross-coupled latch (68) has two cross-coupled inverters (72) and (74) connected thereto such that the master storage node (66) is only connected to one side of the latch (68). The data node (66) directly drives a slave stage comprised of an inverter (76) and transfer gate (78) which in turn drives a slave storage node (80). The slave storage node (80) is connected to a slave cross-coupled latch (82) comprised of cross-coupled inverters (86) and (88). The slave storage node (80) comprises the Q-output of the inverter. The data is transferred to storage node (66) on the negative going edge of the clock signal and latched thereto on the positive going edge of the clock signal. ON the positive going edge of the clock signal, data is transferred from the storage node (66) to the slave storage node (80) and then latched in the latch (82) on the negative going edge of the clock signal. This results in a minimum number of inverters, thus decreasing the Clock-to-Q time.
摘要翻译： 触发器包括用于驱动逆变器（62）和传送门（64）组合以将存储在数据节点（60）上的数据传送到主存储节点（66）的数据存储节点。 主交叉耦合锁存器（68）具有连接到其上的两个交叉耦合的反相器（72）和（74），使得主存储节点（66）仅连接到锁存器（68）的一侧。 数据节点（66）直接驱动由逆变器（76）和传输门（78）组成的从动级，后者又驱动从存储节点（80）。 从存储节点（80）连接到由交叉耦合的反相器（86）和（88）组成的从交叉耦合锁存器（82）。 从存储节点（80）包括逆变器的Q输出。 数据被传送到时钟信号的负向边缘上的存储节点（66），并在时钟信号的正向沿被锁存在存储节点（66）上。 在时钟信号的正向边缘上，数据从存储节点（66）传送到从存储节点（80），然后锁存在时钟信号的负沿的锁存器（82）中。 这导致最小数量的反相器，从而减少了Clock-to-Q时间。
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公开(公告)号：US5390139A
公开(公告)日：1995-02-14
申请号：US69048
申请日：1993-05-28
申请人： Derek Smith , Shivaling Mahant-Shetti , Basavaraj Pawate , George R. Doddington , Warren L. Bean
发明人： Derek Smith , Shivaling Mahant-Shetti , Basavaraj Pawate , George R. Doddington , Warren L. Bean
CPC分类号： G06F17/30982 , G06F12/02
摘要： A memory system 10 is provided including a processor 12 and an active memory device 14 coupled to a processor 12. Active memory 14 includes a first memory 20 for storing a plurality of possible addresses and a second memory 22 for storing an actual address received from processor 12. Circuitry 26 is provided for identifying at least one active address from ones of the possible addresses stored in first memory 20 as a function of the actual address stored in second memory 22.
摘要翻译： 提供存储器系统10，其包括耦合到处理器12的处理器12和有源存储器设备14.活动存储器14包括用于存储多个可能地址的第一存储器20和用于存储从处理器接收的实际地址的第二存储器22 提供电路26，用于根据存储在第二存储器22中的实际地址的函数来识别存储在第一存储器20中的可能地址中的至少一个活动地址。
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公开(公告)号：US5352924A
公开(公告)日：1994-10-04
申请号：US48531
申请日：1993-04-14
IPC分类号： H01L29/06 , H01L29/732 , H01L29/72
CPC分类号： H01L29/7322 , H01L29/0692
摘要： A bipolar transistor is disclosed which substantially reduces prior art problems associated with current crowding by maximizing the active periphery of the transistor's emitter [10].
摘要翻译： 公开了一种双极晶体管，其通过最大化晶体管发射极的有效外围部分，大大减少了与电流拥挤相关的现有技术问题[10]。
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5.发明授权Field programmable gate array logic module configurable as combinational or sequential circuits 失效现场可编程门阵列逻辑模块可配置为组合或顺序电路
公开(公告)号：US5751162A
公开(公告)日：1998-05-12
申请号：US659990
申请日：1996-06-07
申请人： Mahesh Mehendale , Shivaling Mahant-Shetti , Manisha Agarwala , Mark G. Harward , Robert J. Landers
发明人： Mahesh Mehendale , Shivaling Mahant-Shetti , Manisha Agarwala , Mark G. Harward , Robert J. Landers
IPC分类号： H03K19/173
CPC分类号： H03K19/1737
摘要： A logic module 400 for use in a field programmable gate array 100 can be selectively reconfigured to perform over 2,200 boolean combinational functions on output 431, to operate as a full adder with sum and carry outputs, or to perform the sequential function of a D latch or a D flipflop. Logic module 400 is comprised of 2-input multiplexers 500 and 600 which are used to form both the combinational and sequential circuits, thereby efficiently utilizing space on gate array 100.
摘要翻译： 可以选择性地重新配置用于现场可编程门阵列100的逻辑模块400，以在输出端431上执行2200多个布尔组合函数，以作为具有和和和进位输出的全加器运行，或执行D锁存器的顺序功能 或D触发器。 逻辑模块400由用于组合组合电路和顺序电路的2输入多路复用器500和600组成，从而有效利用门阵列100上的空间。
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公开(公告)号：US5500828A
公开(公告)日：1996-03-19
申请号：US474602
申请日：1995-06-07
CPC分类号： G06F15/7821
摘要： An active memory 14 is provided which includes a data memory 20 including rows and columns of storage locations for holding data and computational results. A broadcast memory 22 includes rows and columns of storage locations for holding control instructions. Computing circuitry 26 is provided which is operable to perform a first computational operation using first and second words of data retrieved from the data memory 20 and perform a second computational operation using a result from the first operation and a result from a previous operation. Control circuitry 24 is operable in response to control instructions received from broadcast memory 22 to control the transfer of the first and second words of data from the data memory 20 to said computing circuitry 26 and the performance of the first and second operations.
摘要翻译： 提供了一个活动存储器14，其包括数据存储器20，数据存储器20包括用于保存数据和计算结果的存储位置的行和列。 广播存储器22包括用于保持控制指令的存储位置的行和列。 提供了计算电路26，其可操作以使用从数据存储器20检索的数据的第一和第二字执行第一计算操作，并且使用来自第一操作的结果和来自先前操作的结果执行第二计算操作。 响应于从广播存储器22接收的控制指令来控制数据存储器20中的第一和第二字数据到所述计算电路26以及第一和第二操作的执行，控制电路24可操作。
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7.发明授权Apparatus and method for processing analog signals using residue-based digital operations 失效使用基于残留的数字操作来处理模拟信号的装置和方法
公开(公告)号：US6144329A
公开(公告)日：2000-11-07
申请号：US92691
申请日：1998-06-05
摘要： In apparatus for digital processing to a sequence of numbers in binary format, each number is first converted to a base number and a residue number, the residue number being in a binary bit format. The processing is then performed using only the residue numbers. The digital processing is perfumed using binary addition, binary subtraction, and binary multiplication operations. After completion of the processing operation, the residue numbers are then converted into the original format. The folding analog-to-digital converter can be used to generate the residue binary bit numbers from an analog signal. This technique can reduce the apparatus required to perform such processing operations as FIR filtering and equalization.
摘要翻译： 在用于数字处理的装置中，以二进制格式的数字序列，首先将每个数字转换成一个基数和一个残差号，残差号是二进制位格式。 然后仅使用残基号进行处理。 数字处理使用二进制加法，二进制减法和二进制乘法运算进行加密。 在完成处理操作之后，剩余数字被转换成原始格式。 折叠模数转换器可用于从模拟信号产生残留二进制位数。 该技术可以减少执行FIR滤波和均衡等处理操作所需的设备。
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8.发明授权
公开(公告)号：US5892471A
公开(公告)日：1999-04-06
申请号：US856497
申请日：1997-05-14
CPC分类号： H03M1/0648 , H01L27/0207 , H03M1/742
摘要： A metal-oxide-semiconductor digital-to-analog converter unit includes a multiplicity of current mirror components 20 in a symmetric array, a resistance network activated by voltage sources providing weighted biasing potentials for the current mirror components, and an electrical coupling of the current mirror components to compensate for variations physical properties across converter unit substrate area. The current mirror components 20 include a current steering portion 21.sub.0 -21.sub.N-1 and 25.sub.0 -25.sub.N-1 coupled to an annular bias transistor 22. The resulting digital-to-analog converter has improved performance characteristics when compared to previously implemented digital-to-analog converter units.
摘要翻译： 金属氧化物半导体数模转换器单元包括对称阵列中的多个电流镜组件20，由电压源激活的电阻网络，为电流镜组件提供加权偏置电位，以及电流耦合电流 反射镜组件以补偿变换器单元基板区域上的变化物理性质。 电流镜组件20包括耦合到环形偏置晶体管22的电流转向部分210-21N-1和250-25N-1。与之前实现的数模转换器相比，所得到的数模转换器具有改进的性能特性， 模拟转换器单元。
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公开(公告)号：US5646877A
公开(公告)日：1997-07-08
申请号：US451091
申请日：1995-05-25
CPC分类号： G06F7/5336
摘要： A multiplier and method of multiplying a multiplicand by a multiplier comprising providing a multiplicand of predetermined radix, preferably two, and a predetermined multiple of the multiplicand, preferably three, of the predetermined radix. First and second paths are provided, each path including the multiplicand and the multiple of the multiplicand. One of the multiplicand or multiple of the multiplicand in said first path is selected responsive to the value of the multiplier and one of the multiplicand or multiple of the multiplicand in the second path is selected responsive to the value of the multiplier. The selected multiplicand or multiple of the multiplicand in said first path is left shifted a number of shifts determined by the value of the multiplier and the selected multiplicand or multiple of the multiplicand in the second path is left shifted a number of shifts determined by the value of the multiplier. At least one of the shifted multiplicands or multiples thereof is then assigned one of a positive or negative value as determined by the value of the multiplier and the shifted values are then added together. The circuit also includes an encoder responsive to the value of the multiplier to control the selection of the multiplicand or multiple thereof, the left shifting and the assignment of a positive or negative value. The encoder can include a truth table to assist in performing this function.
摘要翻译： 将被乘数乘以乘法器的乘法器和方法，包括提供预定基数的预定基数，优选为两个的乘法器和预定倍数的预定倍数，优选地三个预定基数。 提供第一和第二路径，每个路径包括被乘数和被乘数的倍数。 响应于乘法器的值来选择所述第一路径中的被乘数之一或被乘数之一，并且响应于乘法器的值来选择第二路径中被乘数中的一个或多个被乘数中的一个。 在所述第一路径中所选择的被乘数或被乘数的倍数是由乘法器的值确定的移位量左移，并且所选择的被乘数或第二路径中被乘数的倍数向左移位由该值确定的多个移位 的乘数。 然后，其中移位的被乘数或其倍数中的至少一个被分配为由乘法器的值确定的正值或负值之一，然后将移位值相加。 电路还包括响应于乘法器的值以控制被乘数或其倍数的选择的编码器，左移位和正值或负值的分配。 编码器可以包括真值表以帮助执行该功能。
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公开(公告)号：US5528549A
公开(公告)日：1996-06-18
申请号：US68908
申请日：1993-05-28
CPC分类号： G06F15/7821
摘要： An active memory 14 is provided which includes a data memory 20 including rows and columns of storage locations for holding data and computational results. A broadcast memory 22 includes rows and columns of storage locations for holding control instructions. Computing circuitry 26 is provided which is operable to perform a first computational operation using first and second words of data retrieved from the data memory 20 and perform a second computational operation using a result from the first operation and a result from a previous operation. Control circuitry 24 is operable in response to control instructions received from broadcast memory 22 to control the transfer of the first and second words of data from the data memory 20 to said computing circuitry 26 and the performance of the first and second operations.
摘要翻译： 提供了一个活动存储器14，其包括数据存储器20，数据存储器20包括用于保存数据和计算结果的存储位置的行和列。 广播存储器22包括用于保持控制指令的存储位置的行和列。 提供了计算电路26，其可操作以使用从数据存储器20检索的数据的第一和第二字执行第一计算操作，并且使用来自第一操作的结果和来自先前操作的结果执行第二计算操作。 响应于从广播存储器22接收的控制指令来控制数据存储器20中的第一和第二字数据到所述计算电路26以及第一和第二操作的执行，控制电路24可操作。
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