公开(公告)号：US20120239778A1

公开(公告)日：2012-09-20

申请号：US13477999

申请日：2012-05-22

申请人： Haihong Wang

发明人： Haihong Wang

IPC分类号： G06F15/16

CPC分类号： G06F17/30174 ,  Y10S707/99952

摘要： Data replication includes generating replication data that is part of a replicated file system to be sent over a communication channel to a destination replication device; adding additional verification information to at least a portion of the replication data to prevent data corruption; and sending the replication data and the additional verification information over the communication channel to the destination replication device. The replication data with additional verification information is sent over the communication channel using a reliable protocol that allows the replication data to be verified by the reliable protocol at the destination replication device. The reliable protocol is a protocol capable of detecting most but not all data corruption introduced by the communication channel. The additional verification information includes information for verifying that replication data sent using the reliable protocol does not include data corruption that was introduced by the communication channel and undetected by the reliable protocol.

摘要翻译： 数据复制包括生成作为通过通信通道发送到目标复制设备的复制文件系统的一部分的复制数据; 向至少一部分复制数据添加其他验证信息，以防止数据损坏; 以及通过所述通信信道将所述复制数据和所述附加验证信息发送到所述目的地复制设备。 具有附加验证信息的复制数据通过通信通道使用可靠协议来发送，该协议允许复制数据由目的地复制设备上的可靠协议进行验证。 可靠的协议是能够检测通信信道引入的大多数但不是全部数据损坏的协议。 附加验证信息包括用于验证使用可靠协议发送的复制数据不包括由通信信道引入并且不被可靠协议检测到的数据损坏的信息。

公开(公告)号：US07422961B2

公开(公告)日：2008-09-09

申请号：US10389456

申请日：2003-03-14

申请人： Haihong Wang ,  Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

发明人： Haihong Wang ,  Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

IPC分类号： H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/823481 ,  H01L29/1054

摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a CVD process.

摘要翻译： 集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。 浅沟槽隔离技术用于应变硅（SMOS）工艺。 用于沟槽的衬垫由半导体或金属层形成，该半导体或金属层在低温过程中沉积，这降低了锗除气。 低温工艺可以是CVD工艺。

公开(公告)号：US07312125B1

公开(公告)日：2007-12-25

申请号：US10773026

申请日：2004-02-05

申请人： Qi Xiang ,  Paul R. Besser ,  Minh Van Ngo ,  Eric N. Paton ,  Haihong Wang

发明人： Qi Xiang ,  Paul R. Besser ,  Minh Van Ngo ,  Eric N. Paton ,  Haihong Wang

IPC分类号： H01L21/336

CPC分类号： H01L29/66772 ,  H01L27/1203 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/7848 ,  H01L29/78621 ,  H01L29/78684 ,  Y10S438/938

摘要： An integrated circuit includes multiple layers. A semiconductor-on-insulator (SOI) wafer can be used to house transistors. Two substrates or wafers can be bonded to form the multiple layers. A strained semiconductor layer can be between a silicon germanium layer and a buried oxide layer. A hydrogen implant can provide a breaking interface to remove a silicon substrate from the silicon germanium layer.

摘要翻译： 集成电路包括多层。 可以使用绝缘体上半导体（SOI）晶片来容纳晶体管。 可以结合两个基板或晶片以形成多个层。 应变半导体层可以在硅锗层和掩埋氧化物层之间。 氢注入可以提供断开界面以从硅锗层去除硅衬底。

公开(公告)号：US06703648B1

公开(公告)日：2004-03-09

申请号：US10282559

申请日：2002-10-29

申请人： Qi Xiang ,  Eric N. Paton ,  Haihong Wang

发明人： Qi Xiang ,  Eric N. Paton ,  Haihong Wang

IPC分类号： H01L2904

CPC分类号： H01L29/6656 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66916 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/802 ,  Y10S438/933

摘要： A strained silicon p-type MOSFET utilizes a strained silicon channel region formed on a silicon germanium substrate. Silicon germanium regions are formed to the silicon germanium layer adjacent to ends of the strained silicon channel region, and shallow source and drain extensions are implanted in the silicon germanium material. The shallow source and drain extensions do not extend into the strained silicon channel region. By forming the source and drain extensions in silicon germanium material rather than in silicon, source and drain extension distortions caused by the enhanced diffusion rate of boron in silicon are avoided.

摘要翻译： 应变硅p型MOSFET利用形成在硅锗衬底上的应变硅沟道区。 硅锗区形成在邻近于应变硅沟道区的端部的硅锗层上，并且浅的源极和漏极延伸部被注入到硅锗材料中。 浅源极和漏极延伸部分不延伸到应变硅沟道区域。 通过在硅锗材料而不是在硅中形成源极和漏极延伸，避免了由硅中的增强的扩散速率引起的源极和漏极扩展失真。

公开(公告)号：US06465267B1

公开(公告)日：2002-10-15

申请号：US09824408

申请日：2001-04-02

申请人： Haihong Wang ,  Qi Xiang

发明人： Haihong Wang ,  Qi Xiang

IPC分类号： H01L2166

CPC分类号： H01L22/12

摘要： The disclosure describes an exemplary method of measuring gate capacitance to determine electrical thickness of a gate dielectric located in a gate structure of a metal oxide semiconductor field effect transistor (MOSFET). This method can include connecting a meter to an integrated circuit gate structure and an active region located proximate the integrated circuit gate structure, applying forward body bias to the transistor to reduce the electrical field of the transistor at a gate inversion measuring point; and measuring capacitance from the meter while the transistor receives the forward body bias.

摘要翻译： 本公开描述了测量栅极电容以确定位于金属氧化物半导体场效应晶体管（MOSFET）的栅极结构中的栅极电介质的电学厚度的示例性方法。 该方法可以包括将仪表连接到集成电路栅极结构和位于集成电路栅极结构附近的有源区，向晶体管施加正向偏置以减小栅极反转测量点处晶体管的电场; 并且当晶体管接收到正向偏置时，测量来自仪表的电容。

公开(公告)号：US07170084B1

公开(公告)日：2007-01-30

申请号：US10872707

申请日：2004-06-21

申请人： Qi Xiang ,  Jung-Suk Goo ,  Haihong Wang

发明人： Qi Xiang ,  Jung-Suk Goo ,  Haihong Wang

IPC分类号： H01L29/06 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L29/66477 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/1054 ,  H01L29/665

摘要： An n-type MOSFET (NMOS) is implemented on a substrate having an epitaxial layer of strained silicon formed on a layer of silicon germanium. The MOSFET includes first halo regions formed in the strained silicon layer that extent toward the channel region beyond the ends of shallow source and drain extensions. Second halo regions formed in the underlying silicon germanium layer extend toward the channel region beyond the ends of the shallow source and drain extensions and extend deeper into the silicon germanium layer than the shallow source and drain extensions. The p-type dopant of the first and second halo regions slows the high rate of diffusion of the n-type dopant of the shallow source and drain extensions through the silicon germanium toward the channel region. By counteracting the increased diffusion rate of the n-type dopant in this manner, the shallow source and drain extension profiles are maintained and the risk of degradation by short channel effects is reduced.

摘要翻译： 在具有形成在硅锗层上的应变硅的外延层的衬底上实施n型MOSFET（NMOS）。 MOSFET包括形成在应变硅层中的第一晕圈，其范围朝向超过浅源极和漏极延伸端的沟道区域。 形成在下面的硅锗层中的第二晕圈延伸到超过浅源极和漏极延伸端的沟道区，并且比浅源极和漏极延伸部更深地延伸到硅锗层中。 第一和第二晕圈区域的p型掺杂剂减缓了浅源极和漏极延伸部分的n型掺杂剂通过硅锗朝向沟道区的高扩散速率。 通过以这种方式抵消增加的n型掺杂剂的扩散速率，维持浅的源极和漏极延伸分布，并且降低由短沟道效应引起的退化的风险。

公开(公告)号：US07001837B2

公开(公告)日：2006-02-21

申请号：US10346617

申请日：2003-01-17

申请人： Minh V. Ngo ,  Paul R. Besser ,  Ming Ren Lin ,  Haihong Wang

发明人： Minh V. Ngo ,  Paul R. Besser ,  Ming Ren Lin ,  Haihong Wang

IPC分类号： H01L21/4763

CPC分类号： H01L29/7843 ,  H01L29/1054 ,  H01L2924/0002 ,  Y10S257/90 ,  Y10S438/933 ,  H01L2924/00

摘要： An exemplary embodiment relates to a method for forming a metal oxide semiconductor field effect transistor (MOSFET). The method includes providing a substrate having a gate formed above the substrate and performing at least one of the following depositing steps: depositing a spacer layer and forming a spacer around a gate and gate insulator located above a layer of silicon above the substrate; depositing an etch stop layer above the spacer, the gate, and the layer of silicon; and depositing a dielectric layer above the etch stop layer. At least one of the depositing a spacer layer, depositing an etch stop layer, and depositing a dielectric layer comprises high compression deposition which increases in tensile strain in the layer of silicon.

摘要翻译： 示例性实施例涉及形成金属氧化物半导体场效应晶体管（MOSFET）的方法。 该方法包括提供一个衬底，该衬底具有形成在衬底上方的栅极，并且执行以下沉积步骤中的至少一个：在位于衬底上方的硅层上方的栅极和栅绝缘体周围沉积间隔层并形成间隔物; 在间隔物，栅极和硅层之上沉积蚀刻停止层; 以及在所述蚀刻停止层上沉积介电层。 沉积间隔层，沉积蚀刻停止层和沉积介电层中的至少一个包括增加硅层中的拉伸应变的高压缩沉积。

公开(公告)号：US06902991B2

公开(公告)日：2005-06-07

申请号：US10282513

申请日：2002-10-24

申请人： Qi Xiang ,  Jung-Suk Goo ,  Haihong Wang

发明人： Qi Xiang ,  Jung-Suk Goo ,  Haihong Wang

IPC分类号： H01L21/20 ,  H01L21/205 ,  H01L21/336 ,  H01L21/337 ,  H01L29/10 ,  H01L21/04

CPC分类号： H01L29/1054 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66795 ,  H01L29/66893

摘要： A strained silicon layer is grown on a layer of silicon germanium and a second layer of silicon germanium is grown on the layer of strained silicon in a single continuous in situ deposition process. Both layers of silicon germanium may be grown in situ with the strained silicon. This construction effectively provides dual substrates at both sides of the strained silicon layer to support the tensile strain of the strained silicon layer and to resist the formation of misfit dislocations that may be induced by temperature changes during processing. Consequently the critical thickness of strained silicon that can be grown on substrates having a given germanium content is effectively doubled. The silicon germanium layer overlying the strained silicon layer may be maintained during MOSFET processing to resist creation of misfit dislocations in the strained silicon layer up to the time of formation of gate insulating material.

摘要翻译： 在硅锗层上生长应变硅层，并且在单个连续原位沉积工艺中，在应变硅层上生长第二层硅锗。 硅锗的两层可以用应变硅原位生长。 这种结构在应变硅层的两侧有效地提供了两个基板，以支撑应变硅层的拉伸应变，并且抵抗可能在加工过程中温度变化引起的失配位错的形成。 因此，可以在具有给定锗含量的衬底上生长的应变硅的临界厚度被有效地加倍。 覆盖应变硅层的硅锗层可以在MOSFET加工过程中保持，以抵抗在形成栅极绝缘材料时产生应变硅层中的失配位错。

公开(公告)号：US06787864B2

公开(公告)日：2004-09-07

申请号：US10335492

申请日：2002-12-31

申请人： Eric N. Paton ,  Qi Xiang ,  Paul R. Besser ,  Ming-Ren Lin ,  Minh V. Ngo ,  Haihong Wang

发明人： Eric N. Paton ,  Qi Xiang ,  Paul R. Besser ,  Ming-Ren Lin ,  Minh V. Ngo ,  Haihong Wang

IPC分类号： H01L2972

CPC分类号： H01L29/4933 ,  H01L21/28052 ,  H01L29/1054 ,  H01L29/4908 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66795 ,  H01L2029/7858

摘要： A MOSFET gate or a MOSFET source or drain region comprises silicon germanium or polycrystalline silicon germanium. Silicidation with nickel is performed to form a nickel germanosilicide that preferably comprises the monosilicide phase of nickel silicide. The inclusion of germanium in the silicide provides a wider temperature range within which the monosilicide phase may be formed, while essentially preserving the superior sheet resistance exhibited by nickel monosilicide. As a result, the nickel germanosilicide is capable of withstanding greater temperatures during subsequent processing than nickel monosilicide, yet provides approximately the same sheet resistance and other beneficial properties as nickel monosilicide.

公开(公告)号：US06756276B1

公开(公告)日：2004-06-29

申请号：US10335522

申请日：2002-12-31

申请人： Qi Xiang ,  Jung-Suk Goo ,  Haihong Wang

发明人： Qi Xiang ,  Jung-Suk Goo ,  Haihong Wang

IPC分类号： H01L21336

CPC分类号： H01L29/66477 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/1054 ,  H01L29/665

摘要： An n-type MOSFET (NMOS) is implemented on a substrate having an epitaxial layer of strained silicon formed on a layer of silicon germanium. The MOSFET includes first halo regions formed in the strained silicon layer that extent toward the channel region beyond the ends of shallow source and drain extensions. Second halo regions formed in the underlying silicon germanium layer extend toward the channel region beyond the ends of the shallow source and drain extensions and extend deeper into the silicon germanium layer than the shallow source and drain extensions. The p-type dopant of the first and second halo regions slows the high rate of diffusion of the n-type dopant of the shallow source and drain extensions through the silicon germanium toward the channel region. By counteracting the increased diffusion rate of the n-type dopant in this manner, the shallow source and drain extension profiles are maintained and the risk of degradation by short channel effects is reduced.

摘要翻译： 在具有形成在硅锗层上的应变硅的外延层的衬底上实施n型MOSFET（NMOS）。 MOSFET包括形成在应变硅层中的第一晕圈，其范围朝向超过浅源极和漏极延伸端的沟道区域。 形成在下面的硅锗层中的第二晕圈延伸到超过浅源极和漏极延伸端的沟道区，并且比浅源极和漏极延伸部更深地延伸到硅锗层中。 第一和第二晕圈区域的p型掺杂剂减缓了浅源极和漏极延伸部分的n型掺杂剂通过硅锗朝向沟道区的高扩散速率。 通过以这种方式抵消增加的n型掺杂剂的扩散速率，维持浅的源极和漏极延伸分布，并且降低由短沟道效应引起的退化的风险。