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71.发明申请SELF-ALIGNED BORDERLESS CONTACTS FOR HIGH DENSITY ELECTRONIC AND MEMORY DEVICE INTEGRATION 有权用于高密度电子和存储器件集成的自对准无边界联系公开(公告)号：US20100038723A1
公开(公告)日：2010-02-18
申请号：US12193339
申请日：2008-08-18
申请人： Katherina E. Babich , Josephine B. Chang , Nicholas C. Fuller , Michael A. Guillorn , Isaac Lauer , Michael J. Rooks
发明人： Katherina E. Babich , Josephine B. Chang , Nicholas C. Fuller , Michael A. Guillorn , Isaac Lauer , Michael J. Rooks
CPC分类号： H01L21/76897 , H01L21/76816 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a transistor having self-aligned borderless electrical contacts is disclosed. A gate stack is formed on a silicon region. An off-set spacer is formed surrounding the gate stack. A sacrificial layer that includes a carbon-based film is deposited overlying the silicon region, the gate stack, and the off-set spacer. A pattern is defined in the sacrificial layer to define a contact area for the electrical contact. The pattern exposes at least a portion of the gate stack and source/drain. A dielectric layer is deposited overlying the sacrificial layer that has been patterned and the portion of the gate stack that has been exposed. The sacrificial layer that has been patterned is selectively removed to define the contact area at the height that has been defined. The contact area for the height that has been defined is metalized to form the electrical contact.
摘要翻译： 公开了一种制造具有自对准无边界电触头的晶体管的方法。 栅极堆叠形成在硅区域上。 在栅堆叠周围形成偏置的间隔物。 包括碳基膜的牺牲层沉积在硅区域，栅极堆叠和偏置间隔物上。 在牺牲层中限定图案以限定电接触的接触面积。 该图案暴露了栅极堆叠和源极/漏极的至少一部分。 沉积覆盖已经图案化的牺牲层和已经暴露的栅极堆叠的部分的电介质层。 已经图案化的牺牲层被选择性地去除以限定已经定义的高度处的接触面积。 已经定义的高度的接触面积被金属化以形成电接触。
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72.发明申请HIGH DENSITY BUTTED JUNCTION CMOS INVERTER, AND MAKING AND LAYOUT OF SAME 审中-公开高密度指针式CMOS反相器，以及其制造和布局公开(公告)号：US20110291193A1
公开(公告)日：2011-12-01
申请号：US12788362
申请日：2010-05-27
CPC分类号： H01L27/1203 , H01L21/26586 , H01L21/823807 , H01L21/823878 , H01L21/84
摘要： A high density, asymmetric, butted junction CMOS inverter, formed on an SOI substrate, may include: an asymmetric p-FET that includes a halo implant on only a source side of the p-FET; an asymmetric n-FET that includes a halo implant on only a source side of the n-FET; and a butted junction comprising an area of said SOI substrate where a drain region of the asymmetric n-FET and a drain region of the asymmetric p-FET are in direct physical contact. Asymmetric halo implants may be formed by a sequential process of covering a first FET of the CMOS inverter with an ion-absorbing structure and applying angled ion radiation to only the source side of the second FET, removing the ion-absorbing structure, covering the first FET with a second ion-absorbing structure, and applying angled ion radiation to only the source side of the second FET. A layout display of CMOS integrated circuit may require one ground rule for the high density, asymmetric butted junction CMOS inverter and another ground rule for other CMOS circuits.
摘要翻译： 形成在SOI衬底上的高密度，不对称对接结CMOS反相器可以包括：非对称p-FET，其仅在p-FET的源极侧包括卤素注入; 一个不对称的n-FET，其仅在n-FET的源极侧包括一个卤素注入; 以及包括所述SOI衬底的区域的对接结，其中所述非对称n-FET的漏极区域和所述非对称p-FET的漏极区域直接物理接触。 可以通过以离子吸收结构覆盖CMOS反相器的第一FET的顺序过程形成非对称晕环植入物，并且仅向第二FET的源极侧施加成角度的离子辐射，去除离子吸收结构，覆盖第一 FET，具有第二离子吸收结构，并且仅向第二FET的源极侧施加成角度的离子辐射。 CMOS集成电路的布局显示可能需要高密度，不对称对接结CMOS反相器和其他CMOS电路的另一个接地规则的一个接地规则。
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公开(公告)号：US20130193513A1
公开(公告)日：2013-08-01
申请号：US13363651
申请日：2012-02-01
IPC分类号： H01L29/786 , G06F17/50 , H01L29/78
CPC分类号： H01L29/785 , H01L29/42376
摘要： A multi-gate field effect transistor apparatus and method for making same. The apparatus includes a source terminal, a drain terminal, and a gate terminal which includes a tapered-gate profile. A method for designing a multi-gate field effect transistor includes arranging a source terminal, a drain terminal and a gate terminal with a tapered-gate profile to create a wider gate width on a bottom of a fin.
摘要翻译： 一种多栅极场效应晶体管装置及其制造方法。 该装置包括源极端子，漏极端子和包括锥形栅极形状的栅极端子。 一种用于设计多栅极场效应晶体管的方法包括：设置具有锥形栅极剖面的源极端子，漏极端子和栅极端子，以在散热片的底部产生更宽的栅极宽度。
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公开(公告)号：US08878298B2
公开(公告)日：2014-11-04
申请号：US13346165
申请日：2012-01-09
CPC分类号： H01L29/7856 , H01L29/66795
摘要： Multiple threshold voltage (Vt) field-effect transistor (FET) devices and techniques for the fabrication thereof are provided. In one aspect, a FET device is provided including a source region; a drain region; at least one channel interconnecting the source and drain regions; and a gate, surrounding at least a portion of the channel, configured to have multiple threshold voltages due to the selective placement of at least one band edge metal throughout the gate.
摘要翻译： 提供了多阈值电压（Vt）场效应晶体管（FET）器件及其制造技术。 一方面，提供一种FET器件，其包括源极区域; 漏区; 将源极和漏极区互连的至少一个沟道; 以及围绕通道的至少一部分的栅极，其被配置为具有多个阈值电压，这是由于至少一个带边缘金属选择性地放置在整个栅极上。
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75.发明授权Graphene devices and semiconductor field effect transistors in 3D hybrid integrated circuits 有权石墨烯装置和3D混合集成电路中的半导体场效应晶体管公开(公告)号：US08748871B2
公开(公告)日：2014-06-10
申请号：US13352737
申请日：2012-01-18
申请人： Phaedon Avouris , Josephine B. Chang , Wilfried E. Haensch , Fei Liu , Zihong Liu , Yanqing Wu , Wenjuan Zhu
发明人： Phaedon Avouris , Josephine B. Chang , Wilfried E. Haensch , Fei Liu , Zihong Liu , Yanqing Wu , Wenjuan Zhu
IPC分类号： H01L27/088
CPC分类号： H01L27/0688 , B82Y10/00 , H01L29/1606 , H01L29/78684
摘要： A three-dimensional integrated circuit includes a semiconductor device, an insulator formed on the semiconductor device, an interconnect formed in the insulator, and a graphene device formed on the insulator.
摘要翻译： 三维集成电路包括半导体器件，形成在半导体器件上的绝缘体，形成在绝缘体中的互连以及形成在绝缘体上的石墨烯器件。
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76.发明授权Techniques for metal gate workfunction engineering to enable multiple threshold voltage FINFET devices 有权金属门功能工程技术可实现多个阈值电压FINFET器件公开(公告)号：US08669167B1
公开(公告)日：2014-03-11
申请号：US13596687
申请日：2012-08-28
IPC分类号： H01L27/092
CPC分类号： H01L27/1211 , H01L21/845
摘要： Techniques are provided for gate work function engineering in FIN FET devices using a work function setting material an amount of which is provided proportional to fin pitch. In one aspect, a method of fabricating a FIN FET device includes the following steps. A SOI wafer having a SOI layer over a BOX is provided. An oxide layer is formed over the SOI layer. A plurality of fins is patterned in the SOI layer and the oxide layer. An interfacial oxide is formed on the fins. A conformal gate dielectric layer, a conformal gate metal layer and a conformal work function setting material layer are deposited on the fins. A volume of the conformal gate metal layer and a volume of the conformal work function setting material layer deposited over the fins is proportional to a pitch of the fins. A FIN FET device is also provided.
摘要翻译： 在Fin FET器件中提供栅极功能工程的技术，其功能设定材料的数量与翅片间距成正比。 一方面，制造FIN FET器件的方法包括以下步骤。 提供了在BOX上具有SOI层的SOI晶片。 在SOI层上形成氧化物层。 在SOI层和氧化物层中图案化多个翅片。 翅片上形成界面氧化物。 共形栅介电层，共形栅极金属层和共形功函数设定材料层沉积在散热片上。 共形栅极金属层的体积和沉积在鳍片上的共形功函数设定材料层的体积与翅片的间距成正比。 还提供了一种FIN FET器件。
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77.发明申请Techniques for Metal Gate Work Function Engineering to Enable Multiple Threshold Voltage Nanowire FET Devices 有权金属栅极工作功能工程技术开启多阈值电压纳米线FET器件公开(公告)号：US20140051213A1
公开(公告)日：2014-02-20
申请号：US13588724
申请日：2012-08-17
IPC分类号： H01L21/336
CPC分类号： H01L29/16 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/068 , H01L29/4232 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： A method of fabricating a nanowire FET device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. Nanowires and pads are etched in the SOI layer. The nanowires are suspended over the BOX. An interfacial oxide is formed surrounding each of the nanowires. A conformal gate dielectric is deposited on the interfacial oxide. A conformal first gate material is deposited on the conformal gate dielectric. A work function setting material is deposited on the conformal first gate material. A second gate material is deposited on the work function setting material to form at least one gate stack over the nanowires. A volume of the conformal first gate material and/or a volume of the work function setting material in the gate stack are/is proportional to a pitch of the nanowires.
摘要翻译： 制造纳米线FET器件的方法包括以下步骤。 提供了具有在BOX上的SOI层的SOI晶片。 在SOI层中蚀刻纳米线和焊盘。 纳米线悬挂在BOX上。 围绕每个纳米线形成界面氧化物。 共形栅电介质沉积在界面氧化物上。 保形第一栅极材料沉积在保形栅极电介质上。 工件功能设定材料沉积在保形第一栅极材料上。 第二栅极材料沉积在功函数设定材料上以在纳米线上形成至少一个栅叠层。 栅极堆叠中的共形第一栅极材料的体积和/或功函数设定材料的体积与纳米线的间距成比例。
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78.发明申请TECHNIQUES FOR GATE WORKFUNCTION ENGINEERING TO REDUCE SHORT CHANNEL EFFECTS IN PLANAR CMOS DEVICES 有权门工功能工程技术降低平面CMOS器件中的短路通道效应公开(公告)号：US20140048882A1
公开(公告)日：2014-02-20
申请号：US13617283
申请日：2012-09-14
IPC分类号： H01L29/78
CPC分类号： H01L29/66545 , H01L21/823842 , H01L21/82385 , H01L21/84 , H01L27/1203
摘要： In one aspect, a CMOS device is provided. The CMOS device includes a SOI wafer having a SOI layer over a BOX; one or more active areas formed in the SOI layer in which one or more FET devices are formed, each of the FET devices having an interfacial oxide on the SOI layer and a gate stack on the interfacial oxide layer, the gate stack having (i) a conformal gate dielectric layer present on a top and sides of the gate stack, (ii) a conformal gate metal layer lining the gate dielectric layer, and (iii) a conformal workfunction setting metal layer lining the conformal gate metal layer. A volume of the conformal gate metal layer and/or a volume of the conformal workfunction setting metal layer present in the gate stack are/is proportional to a length of the gate stack.
摘要翻译： 在一个方面，提供一种CMOS器件。 CMOS器件包括在BOX上具有SOI层的SOI晶片; 形成在其中形成有一个或多个FET器件的SOI层中的一个或多个有源区，每个FET器件在SOI层上具有界面氧化物，在界面氧化物层上具有栅极堆叠，所述栅极堆叠具有（i） 存在于栅极堆叠的顶部和侧面上的共形栅极电介质层，（ii）衬在栅极介电层的共形栅极金属层，以及（iii）在保形栅极金属层之上的共形功函数设定金属层。 存在于栅极堆叠中的共形栅极金属层的体积和/或共形功函数设定金属层的体积与栅极堆叠的长度成比例。
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公开(公告)号：US20130328116A1
公开(公告)日：2013-12-12
申请号：US13490759
申请日：2012-06-07
IPC分类号： H01L27/108 , H01L21/8242 , B82Y99/00
CPC分类号： H01L27/10805 , B82Y10/00 , H01L21/84 , H01L27/0207 , H01L27/10873 , H01L27/1203 , H01L29/0673 , H01L29/66439 , H01L29/775 , H01L29/945 , Y10S977/89 , Y10S977/943
摘要： A semiconductor nanowire is formed integrally with a wraparound semiconductor portion that contacts sidewalls of a conductive cap structure located at an upper portion of a deep trench and contacting an inner electrode of a deep trench capacitor. The semiconductor nanowire is suspended from above a buried insulator layer. A gate dielectric layer is formed on the surfaces of the patterned semiconductor material structure including the semiconductor nanowire and the wraparound semiconductor portion. A wraparound gate electrode portion is formed around a center portion of the semiconductor nanowire and gate spacers are formed. Physically exposed portions of the patterned semiconductor material structure are removed, and selective epitaxy and metallization are performed to connect a source-side end of the semiconductor nanowire to the conductive cap structure.
摘要翻译： 半导体纳米线与环绕半导体部分整体形成，该环绕半导体部分接触位于深沟槽的上部并且与深沟槽电容器的内部电极接触的导电盖结构的侧壁。 半导体纳米线从掩埋绝缘体层的上方悬挂。 在包括半导体纳米线和环绕半导体部分的图案化半导体材料结构的表面上形成栅极电介质层。 围绕半导体纳米线的中心部分形成环形栅电极部分，形成栅极间隔物。 去除图案化的半导体材料结构的物理曝光部分，并且执行选择性外延和金属化以将半导体纳米线的源极端部连接到导电帽结构。
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80.发明授权Graphene devices and silicon field effect transistors in 3D hybrid integrated circuits 有权三维混合集成电路中的石墨烯器件和硅场效应晶体管公开(公告)号：US08587067B2
公开(公告)日：2013-11-19
申请号：US13559941
申请日：2012-07-27
申请人： Josephine B. Chang , Wilfried E. Haensch , Fei Liu , Zihong Liu
发明人： Josephine B. Chang , Wilfried E. Haensch , Fei Liu , Zihong Liu
IPC分类号： H01L27/088
CPC分类号： H01L27/0688 , H01L21/28506 , H01L21/8221 , H01L29/1606 , H01L29/66045 , H01L29/78 , H01L29/78684
摘要： A three dimensional integrated circuit includes a silicon substrate, a first source region disposed on the substrate, a first drain region disposed on the substrate, a first gate stack portion disposed on the substrate, a first dielectric layer disposed on the first source region, the first drain region, the first gate stack portion, and the substrate, a second dielectric layer formed on the first dielectric layer, a second source region disposed on the second dielectric layer, a second drain region disposed on the second dielectric layer, and a second gate stack portion disposed on the second dielectric layer, the second gate stack portion including a graphene layer.
摘要翻译： 三维集成电路包括硅衬底，设置在衬底上的第一源极区域，设置在衬底上的第一漏极区域，设置在衬底上的第一栅极堆叠部分，设置在第一源极区域上的第一电介质层， 第一漏极区域，第一栅极堆叠部分和衬底，形成在第一电介质层上的第二电介质层，设置在第二电介质层上的第二源极区域，设置在第二电介质层上的第二漏极区域，以及第二漏极区域 栅极堆叠部分设置在第二介电层上，第二栅极堆叠部分包括石墨烯层。
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