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公开(公告)号：US20080106715A1
公开(公告)日：2008-05-08
申请号：US11671046
申请日：2007-02-05
Applicant: Burn Jeng Lin , Ching-Yu Chang
Inventor： Burn Jeng Lin , Ching-Yu Chang
IPC: G03B27/42
CPC classification number: G03F7/70866 , G03F7/70341
Abstract: Immersion lithography system and method using a sealed wafer bottom are described. One embodiment is an immersion lithography apparatus comprising a lens assembly comprising an imaging lens and a wafer stage for retaining a wafer beneath the lens assembly, the wafer stage comprising a seal ring disposed on a seal ring frame along a top edge of the wafer retained on the wafer stage, the seal ring for sealing a gap between an edge of the wafer and the wafer stage. The embodiment further includes a fluid tank for retaining immersion fluid, the fluid tank situated with respect to the wafer stage for enabling full immersion of the wafer retained on the wafer stage in the immersion fluid and a cover disposed over at least a portion of the fluid tank for providing a temperature-controlled, fluid-rich environment within the fluid tank; and
Abstract translation: 描述了浸没光刻系统和使用密封晶片底部的方法。 一个实施例是一种浸没光刻设备，其包括透镜组件，该透镜组件包括成像透镜和用于将晶片保持在透镜组件下方的晶片台，晶片台包括沿着晶片的顶部边缘设置在密封环框架上的密封环， 晶片台，用于密封晶片边缘与晶片台之间的间隙的密封环。 该实施例还包括用于保持浸没流体的流体箱，相对于晶片台定位的流体箱，用于使保留在晶片台上的晶片完全浸没在浸没流体中，并且覆盖设置在流体的至少一部分上 罐，用于在流体箱内提供温度控制，流体丰富的环境; 和
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公开(公告)号：US07151593B2
公开(公告)日：2006-12-19
申请号：US11412555
申请日：2006-04-27
Applicant: Burn Jeng Lin
Inventor： Burn Jeng Lin
CPC classification number: G03F1/62 , G03F7/70866 , G03F7/70975 , G03F7/70983 , G03F7/70991
Abstract: A method uses a projection mask aligner that includes a hard pellicle mounting apparatus having an enclosure with an interior cavity, an inlet port for receiving a mask with a protective cover, and an outlet port for outputting a mask covered by a hard pellicle, that has a demounting portion for removing the protective cover from the mask, that has a mounting portion for mounting the hard pellicle on the mask, and that has a conduit for receiving a light-transmitting gas. The method includes: forming a hard pellicle/mask assembly having at least one hard pellicle mounted thereon; positioning the hard pellicle/mask assembly between a light source and an imaging lens; positioning a photoresist-coated semiconductor wafer under the imaging lens with a photoresist layer facing the lens; and imaging microelectronics circuits from the hard pellicle/mask assembly onto the semiconductor wafer.
Abstract translation: 一种方法使用投影掩模对准器，其包括具有具有内腔的外壳的硬膜保护装置，用于接收具有保护盖的掩模的入口端口和用于输出由硬膜覆盖的掩模的出口，所述掩模具有 用于从掩模中去除保护盖的拆卸部分，其具有用于将硬膜安装在掩模上的安装部分，并且具有用于接收透光气体的导管。 该方法包括：形成安装在其上的至少一层硬膜的硬膜/掩模组件; 将硬膜/掩模组件定位在光源和成像透镜之间; 将光致抗蚀剂涂覆的半导体晶片定位在成像透镜下面，其中光致抗蚀剂层面向透镜; 以及将硬膜组件/掩模组件的微电子电路成像到半导体晶片上。
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公开(公告)号：US09330933B2
公开(公告)日：2016-05-03
申请号：US12137259
申请日：2008-06-11
Applicant: Burn Jeng Lin
Inventor： Burn Jeng Lin
IPC: B29C59/02 , H01L21/3105 , H01L21/67
CPC classification number: H01L21/67092 , H01L21/31051 , H01L21/31058
Abstract: A method for planarizing a polymer layer is provided which includes providing a substrate having the polymer layer formed thereon, providing a structure having a substantially flat surface, pressing the flat surface of the structure to a top surface of the polymer layer such that the top surface of the polymer layer substantially conforms to the flat surface of the structure, and separating the flat surface of the structure from the top surface of the polymer material layer.
Abstract translation: 提供了一种用于平面化聚合物层的方法，其包括提供其上形成有聚合物层的基底，提供具有基本平坦表面的结构，将该结构的平坦表面压在聚合物层的顶表面上，使得顶表面 的聚合物层基本上符合结构的平坦表面，并且将结构的平坦表面与聚合物材料层的顶表面分离。
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公开(公告)号：US09182660B2
公开(公告)日：2015-11-10
申请号：US13486000
申请日：2012-06-01
Applicant: Wen-Chuan Wang , Shy-Jay Lin , Jaw-Jung Shin , Burn Jeng Lin
Inventor： Wen-Chuan Wang , Shy-Jay Lin , Jaw-Jung Shin , Burn Jeng Lin
IPC: G03F1/56 , G03F1/78 , H01L21/027 , G03F7/20
CPC classification number: G03F1/56 , G03F1/78 , G03F7/2063 , H01L21/0276 , H01L21/0277
Abstract: A method for electron-beam patterning includes forming a conductive material layer on a substrate; forming a bottom anti-reflective coating (BARC) layer on the conductive material layer; forming a resist layer on the BARC layer; and directing an electron beam (e-beam) to the sensitive resist layer for an electron beam patterning process. The BARC layer is designed such that a top electrical potential of the resist layer is substantially zero during the e-beam patterning process.
Abstract translation: 电子束图案化方法包括在基板上形成导电材料层; 在导电材料层上形成底部抗反射涂层（BARC）层; 在BARC层上形成抗蚀剂层; 并将电子束（电子束）引导到用于电子束图案化工艺的敏感抗蚀剂层。 BARC层被设计成使得在电子束图案化工艺期间抗蚀剂层的顶部电势基本为零。
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公开(公告)号：US08762900B2
公开(公告)日：2014-06-24
申请号：US13534765
申请日：2012-06-27
Applicant: Jaw-Jung Shin , Shy-Jay Lin , Hua-Tai Lin , Burn Jeng Lin
Inventor： Jaw-Jung Shin , Shy-Jay Lin , Hua-Tai Lin , Burn Jeng Lin
IPC: G06F17/50
CPC classification number: G06F17/5081 , G03F1/36 , G03F1/70
Abstract: A method of an integrated circuit (IC) design includes receiving an IC design layout. The IC design layout includes an IC feature with a first outer boundary and a first target points assigned to the first outer boundary. The method also includes generating a second outer boundary for the IC feature and moving all the first target points to the second outer boundary to form a modified IC design layout.
Abstract translation: 集成电路（IC）设计的方法包括接收IC设计布局。 IC设计布局包括具有第一外边界的IC特征和分配给第一外边界的第一目标点。 该方法还包括为IC特征产生第二外部边界并将所有第一目标点移动到第二外部边界以形成修改的IC设计布局。
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Patent Agency Ranking
公开(公告)号：US08722286B2
公开(公告)日：2014-05-13
申请号：US13484588
申请日：2012-05-31
Applicant: Chen-Hua Yu , Jaw-Jung Shin , Shy-Jay Lin , Burn Jeng Lin
Inventor： Chen-Hua Yu , Jaw-Jung Shin , Shy-Jay Lin , Burn Jeng Lin
IPC: G03F1/20
CPC classification number: G03F1/20 , B82Y10/00 , B82Y40/00 , H01J37/045 , H01J37/3175 , H01J37/3177 , H01J2237/31774 , H01J2237/31789 , Y10S430/143
Abstract: A device for reflective electron-beam lithography and methods of producing the same are described. The device includes a substrate, a plurality of conductive layers formed on the substrate, which are parallel to each other and separated by insulating pillar structures, and a plurality of apertures in each conductive layer. Apertures in each conductive layer are vertically aligned with the apertures in other conductive layers and a periphery of each aperture includes conductive layers that are suspended.
Abstract translation: 对反射型电子束光刻装置及其制造方法进行说明。 该装置包括基板，形成在基板上的多个导电层，它们彼此平行并由绝缘柱结构分隔开，并且在每个导电层中形成多个孔。 每个导电层中的孔与其它导电层中的孔垂直对准，并且每个孔的周边包括悬浮的导电层。
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公开(公告)号：US08658344B2
公开(公告)日：2014-02-25
申请号：US13534961
申请日：2012-06-27
Applicant: Chien-Wei Wang , Ching-Yu Chang , Tsai-Sheng Gau , Burn Jeng Lin
Inventor： Chien-Wei Wang , Ching-Yu Chang , Tsai-Sheng Gau , Burn Jeng Lin
CPC classification number: G03F7/0045 , Y10S430/106 , Y10S430/114 , Y10S430/12 , Y10S430/128
Abstract: A resist material and methods using the resist material are disclosed herein. An exemplary method includes forming a resist layer over a substrate, wherein the resist layer includes a polymer, a photoacid generator, an electron acceptor, and a photodegradable base; performing an exposure process that exposes portions of the resist layer with radiation, wherein the photodegradable base is depleted in the exposed portions of the resist layer during the exposure process; and performing an developing process on the resist layer.
Abstract translation: 本文公开了抗蚀剂材料和使用抗蚀剂材料的方法。 一种示例性方法包括在衬底上形成抗蚀剂层，其中抗蚀剂层包括聚合物，光致酸产生剂，电子受体和可光降解的碱; 执行曝光处理，其用辐射曝光抗蚀剂层的一部分，其中光可降解碱在曝光过程中耗尽抗蚀剂层的曝光部分; 并对抗蚀剂层进行显影处理。
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公开(公告)号：US20140007023A1
公开(公告)日：2014-01-02
申请号：US13534765
申请日：2012-06-27
Applicant: Jaw-Jung Shin , Shy-Jay Lin , Hua-Tai Lin , Burn Jeng Lin
Inventor： Jaw-Jung Shin , Shy-Jay Lin , Hua-Tai Lin , Burn Jeng Lin
IPC: G06F17/50
CPC classification number: G06F17/5081 , G03F1/36 , G03F1/70
Abstract: A method of an integrated circuit (IC) design includes receiving an IC design layout. The IC design layout includes an IC feature with a first outer boundary and a first target points assigned to the first outer boundary. The method also includes generating a second outer boundary for the IC feature and moving all the first target points to the second outer boundary to form a modified IC design layout.
Abstract translation: 集成电路（IC）设计的方法包括接收IC设计布局。 IC设计布局包括具有第一外边界的IC特征和分配给第一外边界的第一目标点。 该方法还包括为IC特征产生第二外部边界并将所有第一目标点移动到第二外部边界以形成修改的IC设计布局。
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公开(公告)号：US20130323918A1
公开(公告)日：2013-12-05
申请号：US13486000
申请日：2012-06-01
Applicant: Wen-Chuan Wang , Shy-Jay Lin , Jaw-Jung Shin , Burn Jeng Lin
Inventor： Wen-Chuan Wang , Shy-Jay Lin , Jaw-Jung Shin , Burn Jeng Lin
IPC: H01L21/02
CPC classification number: G03F1/56 , G03F1/78 , G03F7/2063 , H01L21/0276 , H01L21/0277
Abstract: A method for electron-beam patterning includes forming a conductive material layer on a substrate; forming a bottom anti-reflective coating (BARC) layer on the conductive material layer; forming a resist layer on the BARC layer; and directing an electron beam (e-beam) to the sensitive resist layer for an electron beam patterning process. The BARC layer is designed such that a top electrical potential of the resist layer is substantially zero during the e-beam patterning process.
Abstract translation: 电子束图案化方法包括在基板上形成导电材料层; 在导电材料层上形成底部抗反射涂层（BARC）层; 在BARC层上形成抗蚀剂层; 并将电子束（电子束）引导到用于电子束图案化工艺的敏感抗蚀剂层。 BARC层被设计成使得在电子束图案化工艺期间抗蚀剂层的顶部电势基本为零。
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公开(公告)号：US20130320225A1
公开(公告)日：2013-12-05
申请号：US13484588
申请日：2012-05-31
Applicant: Chen-Hua Yu , Jaw-Jung Shin , Shy-Jay Lin , Burn Jeng Lin
Inventor： Chen-Hua Yu , Jaw-Jung Shin , Shy-Jay Lin , Burn Jeng Lin
CPC classification number: G03F1/20 , B82Y10/00 , B82Y40/00 , H01J37/045 , H01J37/3175 , H01J37/3177 , H01J2237/31774 , H01J2237/31789 , Y10S430/143
Abstract: A device for reflective electron-beam lithography and methods of producing the same are described. The device includes a substrate, a plurality of conductive layers formed on the substrate, which are parallel to each other and separated by insulating pillar structures, and a plurality of apertures in each conductive layer. Apertures in each conductive layer are vertically aligned with the apertures in other conductive layers and a periphery of each aperture includes conductive layers that are suspended.
Abstract translation: 对反射型电子束光刻装置及其制造方法进行说明。 该装置包括基板，形成在基板上的多个导电层，它们彼此平行并由绝缘柱结构分隔开，并且在每个导电层中形成多个孔。 每个导电层中的孔与其它导电层中的孔垂直对准，并且每个孔的周边包括悬浮的导电层。
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