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71.发明授权Method and system for incrementally compiling instrumentation into a simulation model 失效将仪器逐步编译成仿真模型的方法和系统公开(公告)号：US06223142B1
公开(公告)日：2001-04-24
申请号：US09190861
申请日：1998-11-09
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A method and system are disclosed that utilize the expressiveness of hardware description languages for incrementally compiling instrumentation logic into a simulation model of a digital circuit design. According to the present invention, a simulation model that includes a design entity file of a digital circuit design is generated. Next, an instrumentation entity file is associated with the design entity file, thereby producing an instrumented design entity file. Finally, and during the process of compiling the simulation model, for the instrumented design entity file: searching for a consistent and previously compiled version of said instrumented design entity file. In response to finding a consistent and previously compiled version, loading the consistent and previously compiled version into the simulation model. In response to finding no consistent and previously compiled version, loading and compiling the instrumented design entity file.
摘要翻译： 公开了一种利用硬件描述语言的表现力来逐步编译仪表逻辑到数字电路设计的仿真模型中的方法和系统。 根据本发明，生成包括数字电路设计的设计实体文件的仿真模型。 接下来，仪器实体文件与设计实体文件相关联，从而生成一个被检测的设计实体文件。 最后，在编译仿真模型的过程中，对于仪表化设计实体文件：搜索一致和先前编译的所述仪表化设计实体文件的版本。 为了找到一致和先前编译的版本，将一致和先前编译的版本加载到仿真模型中。 响应于找不到一致和先前编译的版本，加载和编译仪表化的设计实体文件。
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公开(公告)号：US07840758B2
公开(公告)日：2010-11-23
申请号：US11689990
申请日：2007-03-22
IPC分类号： G06F12/00
CPC分类号： G06F9/3824 , G06F9/30043 , G06F12/0897
摘要： A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue includes a queue entry in which the store queue gathers multiple store operations during a store gathering window to obtain a data portion of a write transaction directed to lower level memory. In addition, the store queue includes dispatch logic that varies a size of the store gathering window to optimize store performance for different store behaviors and workloads.
摘要翻译： 处理器包括执行存储指令以获得存储操作的至少一个指令执行单元和耦合到指令执行单元的存储队列。 存储队列包括队列条目，其中存储队列在存储收集窗口期间收集多个存储操作，以获得指向低级存储器的写入事务的数据部分。 此外，商店队列包括调度逻辑，其改变商店收集窗口的大小以优化针对不同商店行为和工作负载的存储性能。
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73.发明授权Chained cache coherency states for sequential non-homogeneous access to a cache line with outstanding data response 有权链接高速缓存一致性状态用于对具有出色数据响应的高速缓存行的顺序非均匀访问公开(公告)号：US07409504B2
公开(公告)日：2008-08-05
申请号：US11245312
申请日：2005-10-06
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： A method for sequentially coupling successive processor requests for a cache line before the data is received in the cache of a first coupled processor. Both homogenous and non-homogenous operations are chained to each other, and the coherency protocol includes several new intermediate coherency responses associated with the chained states. Chained coherency states are assigned to track the chain of processor requests and the grant of access permission prior to receipt of the data at the first processor. The chained coherency states also identify the address of the receiving processor. When data is received at the cache of the first processor within the chain, the processor completes its operation on (or with) the data and then forwards the data to the next processor in the chain. The chained coherency protocol frees up address bus bandwidth by reducing the number of retries.
摘要翻译： 一种用于在数据在第一耦合处理器的高速缓存中接收数据之前顺序耦合高速缓存行的连续处理器请求的方法。 同质和非均匀的操作彼此链接，并且一致性协议包括与链接状态相关联的几个新的中间一致性响应。 分配链接一致性状态以在第一处理器接收到数据之前跟踪处理器请求链和授予访问权限。 链接的一致性状态还标识接收处理器的地址。 当在链中的第一处理器的高速缓存处接收到数据时，处理器完成其对数据的（或与）数据的操作，然后将数据转发到链中的下一个处理器。 链接的一致性协议通过减少重试次数来释放地址总线带宽。
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74.发明授权Method for priority scheduling and priority dispatching of store conditional operations in a store queue 有权存储条件操作在存储队列中的优先级调度和优先级调度的方法公开(公告)号：US07360041B2
公开(公告)日：2008-04-15
申请号：US10970437
申请日：2004-10-21
IPC分类号： G06F12/00
CPC分类号： G06F9/30087 , G06F9/3004 , G06F9/3824 , G06F9/3834 , G06F9/3851
摘要： A method, system, and processor chip design for reducing the latency between completing a LARX operation and receiving the associated STCX operation to complete the update to the cache line. Each entry of the store queue of the issuing processor is provided an additional tracking bit (priority bit). The priority bit is set whenever a STCX operation is placed within the entry. During selection of an entry for dispatch by the arbitration logic, the arbitration logic scans the value of the priority bits of each eligible entry. An entry with the priority bit set is given priority in the selection process within architectural rules. That entry is then selected for dispatch as early as is possible within the established rules.
摘要翻译： 一种方法，系统和处理器芯片设计，用于减少完成LARX操作和接收相关联的STCX操作之间的延迟，以完成对高速缓存行的更新。 向发行处理器的存储队列的每个条目提供附加跟踪位（优先级位）。 每当在条目中放置STCX操作时，优先级位置位。 在选择由仲裁逻辑发送的条目期间，仲裁逻辑扫描每个合格条目的优先级位的值。 具有优先级位的条目在架构规则中的选择过程中被赋予优先级。 然后在既定规则内尽可能早地选择该条目进行发送。
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75.发明授权Processor, data processing system and method for synchronizing access to data in shared memory 有权处理器，数据处理系统和方法，用于同步共享存储器中数据的访问公开(公告)号：US07228385B2
公开(公告)日：2007-06-05
申请号：US10965113
申请日：2004-10-14
IPC分类号： G06F12/00
CPC分类号： G06F9/3834 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/3851 , G06F12/0811 , G06F12/0831 , G06F12/0855
摘要： A processing unit for a multiprocessor data processing system includes a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, at least one instruction execution unit that executes a store-conditional instruction to determine a store target address, a store queue that, following execution of the store-conditional instruction, buffers a corresponding store operation, sequencer logic associated with the store queue. The sequencer logic, responsive to receipt of a latency indication indicating that resolution of the store-conditional operation as passing or failing is subject to significant latency, invalidates, prior to resolution of the store-conditional operation, a cache line in the store-through upper level cache to which a load-reserve operation previously bound.
摘要翻译： 一种用于多处理器数据处理系统的处理单元，包括存储器上级缓存器，取指令执行指令排序单元，至少一个执行存储条件指令以确定存储目标地址的指令执行单元，存储器 在存储条件指令的执行之后，缓存与存储队列相关联的对应存储操作，定序器逻辑的队列。 定序器逻辑响应于指示存储条件操作的解析作为传递或失败的等待时间指示受到重大等待时间的影响，在存储条件操作的解析之前无效，存储器中的高速缓存行 加载预备操作先前绑定到的高级缓存。
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76.发明授权High speed promotion mechanism suitable for lock acquisition in a multiprocessor data processing system 失效适用于多处理器数据处理系统锁定采集的高速推广机制公开(公告)号：US07213248B2
公开(公告)日：2007-05-01
申请号：US10268729
申请日：2002-10-10
CPC分类号： G06F9/52 , G06F9/3004 , G06F9/30072 , G06F9/30087
摘要： A multiprocessor data processing system includes a plurality of processors coupled to an interconnect and to a global promotion facility containing at least one promotion bit field. A first processor executes a high speed instruction sequence including a load-type instruction to acquire a promotion bit field within the global promotion facility exclusive of at least a second processor. The request may be made visible to all processors coupled to the interconnect. In response to execution of the load-type instruction, a register of the first processor receives a register bit field indicating whether or not the promotion bit field was acquired by execution of the load-type instruction. While the first processor holds the promotion bit field exclusive of the second processor, the second processor is permitted to initiate a request on the interconnect. Advantageously, promotion bit fields are handled separately from data, and the communication of promotion bit fields does not entail the movement of data cache lines.
摘要翻译： 多处理器数据处理系统包括耦合到互连的多个处理器和包含至少一个促销位字段的全局推广设备。 第一处理器执行包括负载型指令的高速指令序列，以在除了至少第二处理器之外的全局促进设备中获取促销位字段。 所述请求可以被耦合到互连的所有处理器可见。 响应于负载型指令的执行，第一处理器的寄存器接收指示通过执行负载型指令是否获取了促销位字段的寄存器位字段。 虽然第一处理器保持不属于第二处理器的升级位字段，但允许第二处理器在互连上发起请求。 优选地，促销比特字段与数据分开处理，并且促销比特字段的通信不需要数据高速缓存行的移动。
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77.发明授权Method, apparatus and system for accessing a global promotion facility through execution of a branch-type instruction 失效通过执行分支式指令访问全球推广工具的方法，装置和系统公开(公告)号：US06925551B2
公开(公告)日：2005-08-02
申请号：US10268742
申请日：2002-10-10
CPC分类号： G06F12/0831 , G06F9/3004 , G06F9/30054 , G06F9/30072 , G06F9/30087
摘要： A multiprocessor data processing system includes first and second processors coupled to an interconnect and to a global promotion facility containing at least one promotion bit field. The first processor initiates execution of a branch-type instruction to request acquisition of a promotion bit field exclusive of at least the second processor. In response to the branch-type instruction, the first processor issues an access request to acquire the promotion bit field. After the accessing request, a register of the first processor receives a register bit indicating whether or not the promotion bit field was successfully acquired by the access request. As a part of executing the branch-type instruction, the first processor selects among a first execution path and a second execution path in response to the register bit.
摘要翻译： 多处理器数据处理系统包括耦合到互连的第一和第二处理器以及包含至少一个促销位字段的全局推广设备。 第一处理器启动分支型指令的执行，以请求获取除了至少第二处理器之外的促销位字段。 响应于分支型指令，第一处理器发出获取促销位字段的访问请求。 在访问请求之后，第一处理器的寄存器接收指示是否通过访问请求成功获取了促销位字段的寄存器位。 作为执行分支型指令的一部分，第一处理器响应于寄存器位在第一执行路径和第二执行路径之中进行选择。
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78.发明授权Speculative execution of instructions and processes before completion of preceding barrier operations 失效完成前面的障碍操作之前，对指令和过程的推测执行公开(公告)号：US06880073B2
公开(公告)日：2005-04-12
申请号：US09753053
申请日：2000-12-28
CPC分类号： G06F9/30087 , G06F9/383 , G06F9/3834 , G06F9/3842
摘要： Described is a data processing system and processor that provides full multiprocessor speculation by which all instructions subsequent to barrier operations in a instruction sequence are speculatively executed before the barrier operation completes on the system bus. The processor comprises a load/store unit (LSU) with a barrier operation (BOP) controller that permits load instructions subsequent to syncs in an instruction sequence to be speculatively issued prior to the return of the sync acknowledgment. Data returned is immediately forwarded to the processor's execution units. The returned data and results of subsequent operations are held temporarily in rename registers. A multiprocessor speculation flag is set in the corresponding rename registers to indicate that the value is “barrier” speculative. When a barrier acknowledge is received by the BOP controller, the flag(s) of the corresponding rename register(s) are reset.
摘要翻译： 描述了提供完整的多处理器推测的数据处理系统和处理器，在系统总线上的屏障操作完成之前，推测性地执行指令序列中的屏障操作之后的所有指令。 处理器包括具有屏障操作（BOP）控制器的加载/存储单元（LSU），其允许在指令序列中的同步之后的加载指令在返回同步确认之前被推测地发出。 返回的数据立即转发到处理器的执行单元。 返回的数据和后续操作的结果暂时保存在重命名寄存器中。 在相应的重命名寄存器中设置多处理器推测标志，以指示该值为“屏障”推测。 当BOP控制器接收到屏障确认时，相应的重命名寄存器的标志被重置。
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79.发明授权System and method for providing multiprocessor speculation within a speculative branch path 失效在推测性分支路径中提供多处理器推测的系统和方法公开(公告)号：US06728873B1
公开(公告)日：2004-04-27
申请号：US09588507
申请日：2000-06-06
IPC分类号： G06F9312
CPC分类号： G06F9/30087 , G06F9/3834 , G06F9/3842
摘要： Disclosed is a method of operation within a processor, that enhances speculative branch processing. A speculative execution path contains an instruction sequence that includes a barrier instruction followed by a load instruction. While a barrier operation associated with the barrier instruction is pending, a load request associated with the load instruction is speculatively issued to memory. A flag is set for the load request when it is speculatively issued and reset when an acknowledgment is received for the barrier operation. Data which is returned by the speculatively issued load request is temporarily held and forwarded to a register or execution unit of the data processing system after the acknowledgment is received. All process results, including data returned by the speculatively issued load instructions are discarded when the speculative execution path is determined to be incorrect.
摘要翻译： 公开了一种处理器内的操作方法，其增强了推测性分支处理。 推测执行路径包含指令序列，其中包含跟随加载指令的障碍指令。 当与障碍指令相关联的障碍操作正在等待时，与加载指令相关联的加载请求被推测地发布到存储器。 当推测性地发出加载请求时设置标志，并且当接收到用于屏障操作的确认时，重置该标志。 在接收到确认之后，由推测发出的加载请求返回的数据被暂时保存并转发到数据处理系统的寄存器或执行单元。 当推测性执行路径被确定为不正确时，所有处理结果（包括由推测发出的加载指令返回的数据）被丢弃。
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80.发明授权公开(公告)号：US06725340B1
公开(公告)日：2004-04-20
申请号：US09588509
申请日：2000-06-06
IPC分类号： G06F9312
CPC分类号： G06F9/30087 , G06F9/3834 , G06F9/3838 , G06F9/3842 , G06F9/3859
摘要： Disclosed is a processor that reduces barrier operations during instruction processing. An instruction sequence includes a first barrier instruction and a second barrier instruction with a store instruction in between the first and second barrier instructions. A store request associated with the store instruction is issued prior to a barrier operation associated with the first barrier instruction. A determination is made of when the store request completes before the first barrier instruction has issued. In response, only a single barrier operation is issued for both the first and second barrier instructions. The single barrier operation is issued after the store request has been issued and at the time the second barrier operation is scheduled to be issued.
摘要翻译： 公开了一种在指令处理期间减少屏障操作的处理器。 指令序列包括在第一和第二屏障指令之间具有存储指令的第一屏障指令和第二屏障指令。 在与第一屏障指令相关联的屏障操作之前发出与存储指令相关联的存储请求。 确定存储请求何时在第一个屏障指令发出之前完成。 作为响应，仅为第一和第二屏障指令发出单个屏障操作。 单个屏障操作在存储请求已经被发出之后并且在第二屏障操作被安排发布的时候发出。
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