公开(公告)号：US07861312B2

公开(公告)日：2010-12-28

申请号：US11668316

申请日：2007-01-29

申请人： Charles C. Lee ,  I-Kang Yu ,  Abraham C. Ma ,  Ming-Shiang Shen

发明人： Charles C. Lee ,  I-Kang Yu ,  Abraham C. Ma ,  Ming-Shiang Shen

IPC分类号： G06F7/04 ,  G06F12/14 ,  G06F21/00 ,  H04L29/06 ,  H04L9/32 ,  H04L9/28 ,  H04N7/167 ,  H04K1/00

CPC分类号： G06F21/32 ,  G06F21/10 ,  G06F2221/2129

摘要： A portable media player receives encrypted audio files and an encrypted content key from a central license server on the Internet. The media player supports digital rights management (DRM) by storing the encrypted audio file in its flash memory and disabling copying or playing of the audio file after a copy limit has been reached. The copy limit is a rule that is combined with the content key in a transfer key that can be encrypted together by the license server. The license server can detect cloning of the media player by reading a unique player ID from the player and detecting when too many accounts use the same unique player ID. The content key can be generated from polar coordinates of the unique player ID, player manufacturer, and song genre. A fingerprint sensor on the player can scan and compare the user's fingerprints to further detect cloning.

摘要翻译： 便携式媒体播放器从互联网上的中央许可证服务器接收加密的音频文件和加密的内容密钥。 媒体播放器通过将加密的音频文件存储在其闪存中来支持数字版权管理（DRM），并且在达到复制限制之后禁用复制或播放音频文件。 复制限制是与许可证服务器可一起加密的传输密钥中的内容密钥相结合的规则。 许可证服务器可以通过从播放器中读取唯一的播放器ID来检测媒体播放器的克隆，并检测何时太多的帐户使用相同的唯一播放器ID。 内容密钥可以由唯一播放器ID，播放器制造商和歌曲类型的极坐标生成。 播放器上的指纹传感器可以扫描并比较用户的指纹，以进一步检测克隆。

公开(公告)号：US07814337B2

公开(公告)日：2010-10-12

申请号：US11623863

申请日：2007-01-17

申请人： Charles C. Lee ,  I-Kang Yu ,  Edward W. Lee ,  Ming-Shiang Shen

发明人： Charles C. Lee ,  I-Kang Yu ,  Edward W. Lee ,  Ming-Shiang Shen

IPC分类号： H04L9/00

CPC分类号： G06F21/85 ,  G06F21/79

摘要： A secure flash-card reader reads a user ID from a secure card and finds a matching entry with a hashed password in a user table on the reader. An encrypted key is received from a secure host that hashes and encrypts a password the user types into the host and the user's ID. A card decryption engine uses a random number to decrypt the encrypted key and recover the hashed password and user ID from the secure host, which is compared by a comparator to the hashed password and user ID from the user table. A mismatch causes an access controller to block access to encrypted data on the secure card. Flash data is transferred over a flash-serial buffer bus between flash-card controllers and a RAM buffer. An encryption engine on the flash-serial buffer bus encrypts and decrypts data and connects to a serial engine to the host.

摘要翻译： 安全的闪存读卡器从安全卡读取用户ID，并在阅读器的用户表中找到具有散列密码的匹配条目。 从安全主机接收加密密钥，该密钥对用户键入的密码和用户的ID进行散列和加密。 卡解密引擎使用随机数来解密加密的密钥，并从安全主机恢复散列密码和用户ID，由比较器与用户表中的散列密码和用户ID进行比较。 不匹配导致访问控制器阻止访问安全卡上的加密数据。 闪存数据通过闪存卡控制器和RAM缓冲区之间的闪存串行缓冲区总线进行传输。 闪存串行缓冲总线上的加密引擎加密和解密数据，并连接到主机的串行引擎。

公开(公告)号：US20100146256A1

公开(公告)日：2010-06-10

申请号：US12651321

申请日：2009-12-31

申请人： Jianjun Luo ,  Chris Tsu ,  Charles C. Lee ,  Ming-Shiang Shen

发明人： Jianjun Luo ,  Chris Tsu ,  Charles C. Lee ,  Ming-Shiang Shen

IPC分类号： G06F15/177 ,  G06F12/00 ,  G06F12/02

CPC分类号： G06F12/1416 ,  G06F12/0638 ,  G06F21/575 ,  G06F21/85 ,  G06F2221/2105 ,  G06K19/07 ,  G06K19/07354

摘要： A Secure Digital (SD) flash microcontroller includes a memory interface to SRAM or DRAM, a flash-memory interface, and a SD interface to an SD bus. The flash memory can be on a flash bus or on the SD bus. The microcontroller is booted from boot code stored in the flash memory. An initial boot loader is read from the first page of flash by a state machine and written to a small RAM. A central processing unit (CPU) in the microcontroller reads instructions from the small RAM, executing the initial boot loader, which reads more pages from flash. These pages are buffered by the small RAM and written to a larger DRAM. Once an extended boot sequence is written to DRAM, the CPU toggles a RAM_BASE bit to cause instruction fetching from DRAM. Then the extended boot sequence is executed from DRAM, copying an OS image from flash to DRAM.

摘要翻译： 安全数字（SD）闪存微控制器包括到SRAM或DRAM的存储器接口，闪存存储器接口和到SD总线的SD接口。 闪存可以在闪存总线或SD总线上。 微控制器从存储在闪存中的引导代码引导。 初始引导加载程序由状态机从闪存的第一页读取并写入小RAM。 微控制器中的中央处理单元（CPU）从小型RAM读取指令，执行初始启动加载程序，从Flash读取更多的页面。 这些页面被小RAM缓冲并写入较大的DRAM。 一旦将扩展引导顺序写入DRAM，CPU将切换一个RAM_BASE位，以使DRAM从DRAM获取指令。 然后从DRAM执行扩展启动顺序，将OS映像从闪存复制到DRAM。

公开(公告)号：US07707354B2

公开(公告)日：2010-04-27

申请号：US11876251

申请日：2007-10-22

申请人： Charles C. Lee ,  David Q. Chow ,  Abraham C. Ma ,  Frank Yu ,  Ming-Shiang Shen

发明人： Charles C. Lee ,  David Q. Chow ,  Abraham C. Ma ,  Frank Yu ,  Ming-Shiang Shen

IPC分类号： G06F12/00

CPC分类号： G06F12/0866 ,  G06F2212/2022 ,  G06F2212/2515

摘要： A flash microcontroller has a Static Random-Access-Memory (SRAM) buffer that stores several blocks of boot code read from a flash memory. The SRAM buffer also operates as a cache of flash data after booting is complete. Cache read and write hits use the SRAM cache rather than flash memory, while old cache lines and read misses access the flash memory. Both the external host and the microcontroller are booted from boot code buffered in the SRAM buffer. A boot-loader state machine reads the flash ID and programs flash parameter registers with timing parameters for the flash memory. The flash microcontroller uses a differential interface to the external host, with a differential transceiver and a differential serial interface. Frame, packet, and encoded clock processing is also performed by the serial interface.

摘要翻译： 闪存微控制器具有静态随机存取存储器（SRAM）缓冲器，其存储从闪存读取的几个引导代码块。 引导完成后，SRAM缓冲区还可以作为闪存数据缓存。 缓存读取和写入命中使用SRAM缓存而不是闪存，而旧的缓存行和读取未命中访问闪存。 外部主机和微控制器均由缓冲在SRAM缓冲区中的引导代码引导。 引导加载器状态机读取闪存ID，并使用Flash存储器的时序参数对闪存参数寄存器进行编程。 闪存单片机使用与外部主机的差分接口，具有差分收发器和差分串行接口。 帧，分组和编码时钟处理也由串行接口执行。

公开(公告)号：US20100027329A1

公开(公告)日：2010-02-04

申请号：US12579695

申请日：2009-10-15

申请人： Charles C. Lee ,  Frank Yu ,  David Q. Chow

发明人： Charles C. Lee ,  Frank Yu ,  David Q. Chow

IPC分类号： G11C11/00 ,  G11C7/10 ,  G11C7/00

CPC分类号： G11C8/08 ,  G11C8/06 ,  G11C8/12 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0085 ,  G11C2213/79

摘要： Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time thus depends on the write data and is relatively long. A page-mode caching PCM device has a lookup table (LUT) that caches write data that is later written to an array of PCM banks. Host data is latched into a line FIFO and written into the LUT, reducing write delays to the relatively slow PCM. Host read data can be supplied by the LUT or fetched from the PCM banks. A multi-line page buffer between the PCM banks and LUT allows for larger block transfers using the LUT. Error-correction code (ECC) checking and generation is performed for data in the LUT, hiding ECC delays for data writes into the PCM banks.

摘要翻译： 相变存储器（PCM）单元使用高电阻非晶和低电阻晶体状态的合金电阻存储数据。 存储单元的设定电流脉冲的时间可以是100 ns，比读取或复位时间长得多。 因此，写入时间取决于写入数据并且相对较长。 页面模式缓存PCM设备具有高速缓存写入数据的查找表（LUT），该数据稍后被写入PCM存储体阵列。 主机数据被锁存到行FIFO中并写入LUT中，从而将写入延迟减少到相对较慢的PCM。 主机读取数据可由LUT提供或从PCM存储区中提取。 PCM组和LUT之间的多行页面缓冲区允许使用LUT进行更大的块传输。 对LUT中的数据执行纠错码（ECC）检查和生成，将ECC数据写入PCM存储体中隐藏ECC延迟。

公开(公告)号：US07610438B2

公开(公告)日：2009-10-27

申请号：US11623860

申请日：2007-01-17

申请人： Charles C. Lee ,  I-Kang Yu ,  Edward W. Lee ,  Ming-Shiang Shen

发明人： Charles C. Lee ,  I-Kang Yu ,  Edward W. Lee ,  Ming-Shiang Shen

IPC分类号： G06F12/06

CPC分类号： G06F12/0868 ,  G06F12/0246 ,  G06F12/0804 ,  G06F2212/2022 ,  G06F2212/214

摘要： A flash-memory cache card caches data that a host writes to a hard disk drive. A flash-memory array has physical blocks of flash memory arranged into first and second data areas having M blocks each, and a wear-leveling-counter pool. An incoming logical sector address (LSA) from a host is mapped to one of M entries in a RAM lookup table using a hash of modulo M. The RAM entry stores a mapping to a physical block in a foreground area that is either the first or the second data area. Pages in the physical block are read for a matching LSA that indicates a cache hit. Full pages are written back to the hard disk and erased in the background while the other data area becomes the foreground area. A new physical block with a low wear-level count is selected from blocks in the new foreground area.

摘要翻译： 闪存缓存卡缓存主机写入硬盘驱动器的数据。 闪存阵列具有布置在每个具有M个块的第一和第二数据区域中的闪存的物理块和磨损平衡计数器池。 来自主机的输入逻辑扇区地址（LSA）被映射到使用模M的散列的RAM查找表中的M个条目之一.RAM条目存储到前景区域中的物理块的映射，该物理块是第一个或 第二个数据区。 对于指示缓存命中的匹配LSA，将读取物理块中的页面。 完整的页面将被写回硬盘并在后台擦除，而另一个数据区域成为前台区域。 从新的前景区域的块中选择具有低磨损级别计数的新物理块。

公开(公告)号：US07552251B2

公开(公告)日：2009-06-23

申请号：US12128916

申请日：2008-05-29

申请人： I-Kang Yu ,  Abraham C. Ma ,  Charles C. Lee

发明人： I-Kang Yu ,  Abraham C. Ma ,  Charles C. Lee

IPC分类号： G06F13/28 ,  G06F9/00

CPC分类号： G06F13/28

摘要： A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.

摘要翻译： 多媒体卡/安全数字（MMC / SD）单芯片闪存设备包含一个MMC / SD闪存微控制器和闪存大容量存储块，其中包含易于寻址的闪存阵列，而不是随机寻址。 来自主机MMC / SD总线的MMC / SD事务由MMC / SD闪存微控制器上的总线收发器读取。 响应于MMC / SD事务中的命令，激活在MMC / SD闪存单片机中的CPU上执行的各种例程。 MMC / SD闪存单片机中的闪存控制器将数据从总线收发器传输到闪存大容量存储块以进行存储。 不是从耦合到CPU的内部ROM引导，引导加载程序由DMA从闪存大容量存储块的第一页传输到内部RAM。 在上电时，闪存将从第一页自动读取。 CPU然后从内部RAM执行引导加载程序来加载控制程序。

公开(公告)号：US20080320214A1

公开(公告)日：2008-12-25

申请号：US12186471

申请日：2008-08-05

申请人： Abraham C. Ma ,  David Q. Chow ,  Charles C. Lee ,  Frank Yu

发明人： Abraham C. Ma ,  David Q. Chow ,  Charles C. Lee ,  Frank Yu

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F3/0613 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0658 ,  G06F3/0664 ,  G06F3/0688 ,  G06F2212/7201 ,  G06F2212/7208 ,  G06F2212/7211 ,  G11C13/0004

摘要： A solid-state disk (SSD) has a smart storage switch with a smart storage transaction manager that re-orders host commands for accessing downstream single-chip flash-memory devices. Each single-chip flash-memory device has a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory blocks in the single-chip flash-memory device. Wear-leveling and bad block remapping are preformed by each single-chip flash-memory device, and at a higher level by a virtual storage processor in the smart storage switch. Virtual storage bridges between the smart storage transaction manager and the single-chip flash-memory devices bridge LBA transactions over LBA buses to the single-chip flash-memory devices. Data striping and interleaving among multiple channels of the single-chip flash-memory device is controlled at a high level by the smart storage transaction manager, while further interleaving and remapping may be performed within each single-chip flash-memory device.

摘要翻译： 固态磁盘（SSD）具有智能存储交换机，智能存储交易管理器重新命令用于访问下游单芯片闪存设备的主机命令。 每个单芯片闪存设备具有将逻辑块地址（LBA）转换为访问单芯片闪存设备中的闪存块的物理块地址（PBA）的较低级别的控制器。 磨损均衡和坏块重映射由每个单芯片闪存设备执行，并且在智能存储交换机中的虚拟存储处理器处于更高级别。 智能存储事务管理器和单芯片闪存设备之间的虚拟存储网桥将LBA总线上的LBA交易桥接到单芯片闪存设备。 单芯片闪速存储器件的多个通道之间的数据条带化和交错由智能存储事务管理器控制在高电平，而可以在每个单芯片闪速存储器件内执行进一步的交错和重新映射。

公开(公告)号：US20080313389A1

公开(公告)日：2008-12-18

申请号：US11929799

申请日：2007-10-30

申请人： David Q. Chow ,  Frank I. Yu ,  Charles C. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

发明人： David Q. Chow ,  Frank I. Yu ,  Charles C. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G06F2212/7202 ,  G06F2212/7208 ,  G06K9/00087 ,  G06K19/07 ,  G06K19/07354 ,  G07C9/00087

摘要： An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming.

公开(公告)号：US20080235939A1

公开(公告)日：2008-10-02

申请号：US12033851

申请日：2008-02-19

申请人： Siew S. Hiew ,  Charles C. Lee ,  Paul Hsueh ,  Abraham C. Ma ,  Ming-Shiang Shen

发明人： Siew S. Hiew ,  Charles C. Lee ,  Paul Hsueh ,  Abraham C. Ma ,  Ming-Shiang Shen

IPC分类号： H05K3/20 ,  G11C11/34

CPC分类号： H05K3/284 ,  H01L21/561 ,  H01L24/97 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/1815 ,  H05K1/117 ,  H05K3/0032 ,  H05K3/0052 ,  H05K2201/09154 ,  H05K2201/10159 ,  H05K2203/0228 ,  H05K2203/0746 ,  H05K2203/1316 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49146 ,  Y10T29/49147 ,  Y10T29/49171 ,  Y10T29/49789 ,  Y10T29/49798 ,  H01L2224/85 ,  H01L2924/00

摘要： A method for fabricating MicroSD devices includes forming a PCB panel having multiple PCB regions arranged in parallel rows. Passive components are attached by conventional surface mount technology (SMT) techniques. IC chips, including a MicroSD controller chip and a flash memory chip, are attached to the PCB by wire bonding or other chip-on-board (COB) technique. A molded layer is then formed over the IC chips and passive components using a mold that prevents formation of plastic on the upper surface of each PCB. The panel is then singulated using one of a laser cutting method, an abrasive water jet cutting method, and a mechanical grinding method such that the resulting PCB substrate and plastic housing have the width, height and length specified by MicroSD specifications. A front edge chamfer process is then performed.

摘要翻译： 一种用于制造MicroSD器件的方法包括形成具有平行排布置的多个PCB区域的PCB面板。 无源元件通过常规表面贴装技术（SMT）技术连接。 包括MicroSD控制器芯片和闪存芯片在内的IC芯片通过引线接合或其他芯片上的（COB）芯片技术连接到PCB。 然后使用防止在每个PCB的上表面上形成塑料的模具在IC芯片和无源部件上形成模制层。 然后使用激光切割方法，磨料水射流切割方法和机械研磨方法之一将面板切片，使得所得PCB基板和塑料外壳具有由MicroSD规格规定的宽度，高度和长度。 然后执行前沿倒角处理。