公开(公告)号：US06440850B1

公开(公告)日：2002-08-27

申请号：US09385586

申请日：1999-08-27

申请人： Kunal R. Parekh ,  Mark Fischer ,  Charles H. Dennison

发明人： Kunal R. Parekh ,  Mark Fischer ,  Charles H. Dennison

IPC分类号： H01L2144

CPC分类号： H01L23/485 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

摘要： A network of electrically conductive plate contacts is provided within the structure of a DRAM chip to enable storage of non-zero voltage levels in each charge storage region. An improved cell or top plate contact provides low contact resistance and improved structural integrity making the contact less prone to removal during subsequent processing steps. A top plate conformally lines a container patterned down into a subregion. A metal contact structure comprises a waist section, a contact leg, and an anchor leg. The contact leg makes contact to the top plate within the container interior. The waist section joins the top of the contact leg to the top of the anchor leg and extends over the edge of the top plate. The anchor leg extends downward through the subregion adjacent to but spaced from the container to anchor the structure in place and provide structural integrity. Accordingly, the present invention provides an improved structure for contact to a conductive thin film, having low contact resistance and an improved structural integrity.

摘要翻译： 在DRAM芯片的结构内提供导电板触点的网络，以便能够在每个电荷存储区域中存储非零电压电平。 改进的电池或顶板接触提供低接触电阻和改进的结构完整性，使得接触在随后的加工步骤期间更不易于去除。 顶板共形地将图案化的容器图案化成一个子区域。 金属接触结构包括腰部，接触腿和锚腿。 接触腿与容器内部的顶板接触。 腰部将接触腿的顶部连接到锚腿的顶部并且在顶板的边缘上延伸。 锚腿向下延伸穿过与容器相邻但与容器间隔开的子区域，以将结构锚定在适当位置并提供结构完整性。 因此，本发明提供了一种与导电薄膜接触的改进的结构，具有低的接触电阻和改进的结构完整性。

公开(公告)号：US06376358B1

公开(公告)日：2002-04-23

申请号：US09809666

申请日：2001-03-15

申请人： Mark Fischer ,  Jigish D. Trivedi ,  Charles H. Dennison ,  Todd R. Abbott ,  Raymond A. Turi

发明人： Mark Fischer ,  Jigish D. Trivedi ,  Charles H. Dennison ,  Todd R. Abbott ,  Raymond A. Turi

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  G11C2207/104 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10888

摘要： A process for fabricating system-on-chip devices which contain embedded DRAM along with other components such as SRAM or logic circuits is disclosed. Local interconnects, via salicides and tungsten are formed subsequent to polysilicon plugs required for the operation of the DRAM and SRAM or logic. Also disclosed are systems-on-chips MIM/MIS capacitive devices produced by the inventive process.

公开(公告)号：US06331725B1

公开(公告)日：2001-12-18

申请号：US08951854

申请日：1997-10-16

申请人： Charles H. Dennison

发明人： Charles H. Dennison

IPC分类号： H01L2976

CPC分类号： H01L27/10852

摘要： A semiconductor processing method of forming a contact pedestal includes, a) providing a node location to which electrical connection is to be made; b) providing insulating dielectric material over the node location; c) etching a contact opening into the insulating dielectric material over the node location to a degree insufficient to outwardly expose the node location, the contact opening having a base; d) providing a spacer layer over the insulating dielectric material to within the contact opening to a thickness which less than completely fills the contact opening; e) anisotropically etching the spacer layer to form a sidewall spacer within the contact opening; f) after forming the sidewall spacer, etching through the contact opening base to outwardly expose the node location; g) filling the contact opening to the node location with electrically conductive material; h) rendering the sidewall spacer electrically conductive; and i) etching the electrically conductive material to form an electrically conductive contact pedestal comprising the sidewall spacer, the pedestal having an outer surface which is substantially coplanar with opposing laterally adjacent electrically insulative surfaces. Also disclosed is integrated circuitry including contact pedestals. Also disclosed are methods of forming storage nodes of capacitors.

摘要翻译： 形成接触基座的半导体处理方法包括：a）提供要进行电连接的节点位置; b）在节点位置上提供绝缘电介质材料; c）在所述节点位置上将接触开口蚀刻到所述绝缘介电材料中至不足以向外暴露所述节点位置的程度，所述接触开口具有基部; d）在绝缘电介质材料之上提供间隔层至接触开口内至少小于完全填充接触开口的厚度; e）各向异性地蚀刻间隔层以在接触开口内形成侧壁间隔物; f）在形成侧壁间隔物之后，通过接触开口基底蚀刻以向外暴露节点位置; g）用导电材料将接触开口填充到节点位置; h）使侧壁间隔物导电; 以及i）蚀刻所述导电材料以形成包括所述侧壁间隔物的导电接触基座，所述基座具有与相对的横向相邻的电绝缘表面基本上共面的外表面。 还公开了包括接触基座的集成电路。 还公开了形成电容器的存储节点的方法。

公开(公告)号：US06323087B1

公开(公告)日：2001-11-27

申请号：US09565196

申请日：2000-05-04

申请人： Charles H. Dennison

发明人： Charles H. Dennison

IPC分类号： H01L218247

CPC分类号： H01L23/485 ,  H01L21/76802 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming contact openings, making electrical interconnections, and related integrated circuitry are described. Integrated circuitry formed through one or more of the inventive methodologies is also described. In one implementation, a conductive runner or line having a contact pad with which electrical communication is desired is formed over a substrate outer surface. A conductive plug is formed laterally proximate the contact pad and together therewith defines an effectively widened contact pad. Conductive material is formed within a contact opening which is received within insulative material over the effectively widened contact pad. In a preferred implementation, a pair of conductive plugs are formed on either side of the contact pad laterally proximate thereof. The conductive plug(s) can extend away from the substrate outer surface a distance which is greater or less than a conductive line height of a conductive line adjacent which the plug is formed. In the former instance and in accordance with one aspect, such plug(s) can include a portion which overlaps with the contact pad of the associated conductive line.

公开(公告)号：US06261948B1

公开(公告)日：2001-07-17

申请号：US09285322

申请日：1999-04-02

申请人： Charles H. Dennison

发明人： Charles H. Dennison

IPC分类号： H01L214763

CPC分类号： H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a contact opening is described and which includes providing a node location to which electrical connection is to be made; forming a conductive line adjacent the node location, the conductive line having a conductive top and sidewall surfaces; forming electrically insulative oxide in covering relation relative to the top surface of the conductive line; forming electrically insulative nitride sidewall spacers over the conductive sidewall surfaces, the nitride sidewall spacers projecting outwardly of the conductive line top conductive surface, the electrically insulative oxide positioned between the nitride sidewall spacers; forming an electrically insulative layer outwardly of the conductive line, and the node location; and etching a contact opening to the node location or the top surface through the electrically insulative layer substantially selective relative to the nitride sidewall spacers.

公开(公告)号：US06233190B1

公开(公告)日：2001-05-15

申请号：US09386075

申请日：1999-08-30

申请人： Christopher B. Cooper ,  Ming-Bo Liu ,  Chris G. Martin ,  Troy A. Manning ,  Stephen L. Casper ,  Charles H. Dennison ,  Brian M. Shirley ,  Brian L. Brown ,  Shubneesh Batra

发明人： Christopher B. Cooper ,  Ming-Bo Liu ,  Chris G. Martin ,  Troy A. Manning ,  Stephen L. Casper ,  Charles H. Dennison ,  Brian M. Shirley ,  Brian L. Brown ,  Shubneesh Batra

IPC分类号： G11C704

CPC分类号： G11C7/04 ,  G11C7/1045 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4078

摘要： A method for storing a temperature threshold in an integrated circuit includes measuring operating parameters of the integrated circuit versus temperature, calculating a maximum temperature at which the integrated circuit performance exceeds predetermined specifications and storing parameters corresponding to the maximum temperature in a comparison circuit in the integrated circuit by selectively blowing fusable devices in the comparison circuit. The fusable devices may be antifuses. As a result, the integrated circuit is able to provide signals to devices external to the integrated circuit to indicate that the integrated circuit may be too hot to operate properly.

摘要翻译： 一种用于在集成电路中存储温度阈值的方法包括：测量集成电路的相对于温度的操作参数，计算集成电路性能超过预定规格的最大温度，并将集成电路性能中最高温度的参数存储在集成电路中的比较电路中 通过在比较电路中选择性地吹入可熔设备。 可熔断器件可以是反熔丝。 因此，集成电路能够向集成电路外部的设备提供信号，以指示集成电路可能太热而无法正常工作。

公开(公告)号：US06200842B1

公开(公告)日：2001-03-13

申请号：US09547194

申请日：2000-04-11

申请人： Trung Tri Doan ,  Charles H. Dennison

发明人： Trung Tri Doan ,  Charles H. Dennison

IPC分类号： H01L218238

CPC分类号： H01L21/82385 ,  H01L21/823842

摘要： A method of forming complementary type conductive regions on a substrate includes, a) providing a first etch stop layer over a substrate; b) etching a void through the first etch stop layer inwardly towards the substrate; c) providing a first conductive layer of a first conductive material over the first etch stop layer and into the void; d) removing the first conductive layer over the first etch stop layer to eliminate all first conductive material from atop the first etch stop layer, and leaving first conductive material in the void; e) removing the remaining first etch stop layer from the substrate thereby defining a remaining region of first conductive layer; f) providing a second conductive layer of a second conductive material over the substrate and remaining first conductive layer region; and g) removing the second conductive layer over the first conductive layer to eliminate all second conductive material from atop the first conductive layer, and leaving second conductive material atop the substrate which is adjacent the projecting first conductive material region.

摘要翻译： 在衬底上形成互补型导电区域的方法包括：a）在衬底上提供第一蚀刻停止层; b）通过第一蚀刻停止层向衬底内部蚀刻空隙; c）在所述第一蚀刻停止层上并在所述空隙中提供第一导电材料的第一导电层; d）去除第一蚀刻停止层上的第一导电层，以从第一蚀刻停止层顶部消除所有第一导电材料，并将第一导电材料留在空隙中; e）从衬底去除剩余的第一蚀刻停止层，从而限定第一导电层的剩余区域; f）在所述衬底上提供第二导电材料的第二导电层和剩余的第一导电层区域; 以及g）在所述第一导电层之上移除所述第二导电层以从所述第一导电层顶部消除所有第二导电材料，并且在所述基板的顶部与所述突出的第一导电材料区域相邻处留下第二导电材料。

公开(公告)号：US06184096B2

公开(公告)日：2001-02-06

申请号：US09276976

申请日：1999-03-26

申请人： Roger R. Lee ,  Charles H. Dennison

发明人： Roger R. Lee ,  Charles H. Dennison

IPC分类号： H01L21336

CPC分类号： H01L21/76216 ,  H01L21/823418 ,  H01L21/823878

摘要： A semiconductor processing method of providing dopant impurity into a semiconductor substrate includes: a) providing a semiconductor substrate, the substrate comprising a first bulk region having a blanket doping of a first conductivity type dopant, the substrate comprising a second bulk region having a blanket doping of a second conductivity type dopant; b) defining field oxide regions and active area regions in each of the first and second bulk substrate regions; c) in the same masking step, masking active area regions of the first bulk substrate region while leaving field oxide regions of the first bulk substrate region unmasked and masking field oxide regions of the second bulk substrate region while leaving select active area regions of the second bulk substrate region unmasked; and d) in the same ion implanting step, ion implanting first conductivity type impurity through the unmasked portions of the first and second bulk substrate regions to simultaneously form channel stop isolation implants beneath the unmasked field oxide regions in the first bulk substrate region and electrically conductive active area implants in the unmasked active area regions of the second bulk substrate region.

摘要翻译： 向半导体衬底提供掺杂杂质的半导体处理方法包括：a）提供半导体衬底，该衬底包括具有第一导电类型掺杂剂的覆盖掺杂的第一体区，该衬底包括具有覆盖掺杂的第二体区 的第二导电型掺杂剂; b）限定所述第一和第二体基板区域中的每一个中的场氧化物区域和有源区域区域; c）在相同的掩蔽步骤中，掩蔽所述第一体基板区域的有源区域区域，同时保留所述第一体基板区域的场氧化物区域未掩蔽并掩蔽所述第二体基板区域的场氧化物区域，同时留下所述第二体基板区域的选择有源区域区域 散装衬底区域未屏蔽; 以及d）在相同的离子注入步骤中，通过第一和第二体衬底区域的未屏蔽部分离子注入第一导电类型杂质，以同时在第一体衬底区域中未掩模的场氧化物区域下面形成沟道截止隔离植入物，并且导电 在第二体基板区域的未掩蔽的有源区域区域中的有源区植入。

公开(公告)号：US6140219A

公开(公告)日：2000-10-31

申请号：US127577

申请日：1998-07-31

申请人： Charles H. Dennison

发明人： Charles H. Dennison

IPC分类号： H01L21/8242 ,  H01L23/485 ,  H01L29/417 ,  H01L21/4763 ,  H01L21/3205

CPC分类号： H01L27/10873 ,  H01L23/485 ,  H01L29/41725 ,  H01L2924/0002 ,  Y10S257/90 ,  Y10S257/906

摘要： A method for forming a contact opening is described and which includes providing a node location to which electrical connection is to be made; forming a conductive line adjacent the node location, the conductive line having a conductive top and sidewall surfaces; forming electrically insulative oxide in covering relation relative to the top surface of the conductive line; forming electrically insulative nitride sidewall spacers over the conductive sidewall surfaces, the nitride sidewall spacers projecting outwardly of the conductive line top conductive surface, the electrically insulative oxide positioned between the nitride sidewall spacers; forming an electrically insulative layer outwardly of the conductive line, and the node location; and etching a contact opening to the node location or the top surface through the electrically insulative layer substantially selective relative to the nitride sidewall spacers.

摘要翻译： 描述了一种用于形成接触开口的方法，其包括提供将要进行电连接的节点位置; 在所述节点位置附近形成导线，所述导电线具有导电顶部和侧壁表面; 形成相对于导电线的顶表面的覆盖关系的电绝缘氧化物; 在所述导电侧壁表面上形成电绝缘氮化物侧壁隔离物，所述氮化物侧壁间隔物从所述导电线顶部导电表面向外突出，所述电绝缘氧化物位于所述氮化物侧壁间隔物之间​​; 在导电线外部形成电绝缘层，以及节点位置; 以及通过所述电绝缘层蚀刻到所述节点位置或所述顶表面的接触开口，所述电绝缘层相对于所述氮化物侧壁间隔件基本上是选择性的。

公开(公告)号：US6124616A

公开(公告)日：2000-09-26

申请号：US49282

申请日：1998-03-26

申请人： Charles H. Dennison ,  Mark Helm

发明人： Charles H. Dennison ,  Mark Helm

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L27/105 ,  H01L29/76

CPC分类号： H01L21/823807 ,  H01L27/0922 ,  H01L27/105

摘要： A method of forming CMOS integrated circuitry includes, a) providing a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to an area of the substrate for formation of an NMOS transistor, a second gate line being positioned relative to an area of the substrate for formation of a PMOS transistor; b) masking the second gate line and the PMOS substrate area while conducting a p-type halo ion implant into the NMOS substrate area adjacent the first gate line, the p-type halo ion implant being conducted at a first energy level to provide a p-type first impurity concentration at a first depth within the NMOS substrate area; and c) in a common step, blanket ion implanting phosphorus into both the NMOS substrate area and the PMOS substrate area adjacent the first and the second gate lines to form both NMOS LDD regions and PMOS n-type halo regions, respectively, the phosphorus implant being conducted at a second energy level to provide an n-type second impurity concentration at a second depth within both the PMOS substrate area and the NMOS substrate area, the first energy level and the first depth being greater than the second energy level and the second depth, respectively. Methods of forming memory and other CMOS integrated circuitry are also disclosed involving optimization of different NMOS transistors.

摘要翻译： 一种形成CMOS集成电路的方法包括：a）在半导体衬底上提供一系列栅极线，第一栅极线相对于衬底的区域定位以形成NMOS晶体管，第二栅极线相对于 用于形成PMOS晶体管的衬底的区域; b）在将p型卤素离子注入进入与第一栅极线相邻的NMOS衬底区域的同时掩蔽第二栅极线和PMOS衬底区域，p型卤素离子注入以第一能级进行，以提供p 在NMOS衬底区域内的第一深度处的第一杂质浓度; 和c）在共同的步骤中，将磷离子注入到与第一和第二栅极线相邻的NMOS衬底区域和PMOS衬底区域中，分别形成NMOS LDD区和PMOS n型晕区，磷植入 在第二能级进行，以在PMOS衬底区域和NMOS衬底区域内的第二深度处提供n型第二杂质浓度，第一能级和第一深度大于第二能级，第二级 深度。 还公开了形成存储器和其它CMOS集成电路的方法，其涉及不同NMOS晶体管的优化。