公开(公告)号：US08341497B2

公开(公告)日：2012-12-25

申请号：US12713631

申请日：2010-02-26

申请人： Kazuhiro Fukutomi ,  Hideaki Sato ,  Shinichi Kanno ,  Shigehiro Asano

发明人： Kazuhiro Fukutomi ,  Hideaki Sato ,  Shinichi Kanno ,  Shigehiro Asano

IPC分类号： G11C29/00 ,  G06F11/00

CPC分类号： G06F11/108 ,  G06F11/1052

摘要： A semiconductor storage includes a receiver configured to receive a write request from a host device; a storage unit configured to hold redundancy data generation/non-generation information; a writing unit configured to write data in a semiconductor memory array and write redundancy data generation/non-generation information of the written data in the storage unit; a first data extracting unit configured to extract data whose redundancy data is not generated from among the data held by the semiconductor memory array; a first redundancy data generating unit configured to generate redundancy data; a first redundancy data writing unit configured to write the generated redundancy data in the semiconductor memory array; and a first redundancy data generation/non-generation information updating unit configured to update the redundancy data generation/non-generation information of the data whose redundancy data held by the storage unit is generated.

摘要翻译： 半导体存储器包括被配置为从主机设备接收写请求的接收器; 存储单元，被配置为保存冗余数据生成/非生成信息; 写入单元，被配置为在半导体存储器阵列中写入数据，并将写入的数据的冗余数据生成/非生成信息写入存储单元中; 第一数据提取单元，被配置为从半导体存储器阵列保存的数据中提取不产生冗余数据的数据; 第一冗余数据生成单元，被配置为生成冗余数据; 第一冗余数据写入单元，被配置为将所生成的冗余数据写入所述半导体存储器阵列中; 以及第一冗余数据生成/非生成信息更新单元，被配置为更新由所述存储单元保持的冗余数据生成的数据的冗余数据生成/非生成信息。

公开(公告)号：US08219861B2

公开(公告)日：2012-07-10

申请号：US13270788

申请日：2011-10-11

申请人： Toshikatsu Hida ,  Shinichi Kanno ,  Hirokuni Yano ,  Kazuya Kitsunai ,  Shigehiro Asano ,  Junji Yano

发明人： Toshikatsu Hida ,  Shinichi Kanno ,  Hirokuni Yano ,  Kazuya Kitsunai ,  Shigehiro Asano ,  Junji Yano

IPC分类号： G11C29/00

CPC分类号： G06F11/1412 ,  G06F11/1068 ,  G06F11/1402 ,  G06F12/02 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431

摘要： As a semiconductor storage device that can efficiently perform a refresh operation, provided is a semiconductor storage device comprising a non-volatile semiconductor memory storing data in blocks, the block being a unit of data erasing, and a controlling unit monitoring an error count of data stored in a monitored block selected from the blocks and refreshing data in the monitored block in which the error count is equal to or larger than a threshold value.

摘要翻译： 作为可以有效地执行刷新操作的半导体存储装置，提供了一种半导体存储装置，其包括以块为单位存储数据的非易失性半导体存储器，该块是数据擦除单元，以及监视数据的错误计数的控制单元 存储在从所述块中选择的监视块和所述监视块中的刷新数据中，其中所述错误计数等于或大于阈值。

公开(公告)号：US08060797B2

公开(公告)日：2011-11-15

申请号：US12529282

申请日：2008-09-22

申请人： Toshikatsu Hida ,  Shinichi Kanno ,  Hirokuni Yano ,  Kazuya Kitsunai ,  Shigehiro Asano ,  Junji Yano

发明人： Toshikatsu Hida ,  Shinichi Kanno ,  Hirokuni Yano ,  Kazuya Kitsunai ,  Shigehiro Asano ,  Junji Yano

IPC分类号： G06F11/00

CPC分类号： G06F11/1412 ,  G06F11/1068 ,  G06F11/1402 ,  G06F12/02 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431

摘要： A semiconductor storage device can efficiently perform a refresh operation. A semiconductor storage device is provided which includes a non-volatile semiconductor memory storing data in blocks, the block being a unit of data erasing. A controlling unit is further included monitoring an error count of data stored in a monitored block selected from the blocks and for refreshing data in the monitored block in which the error count is equal to or larger than a threshold value.

摘要翻译： 半导体存储装置可以有效地执行刷新操作。 提供一种半导体存储装置，其包括以块为单位存储数据的非易失性半导体存储器，该块是数据擦除的单位。 还包括控制单元，用于监视存储在从块中选择的监视块中的数据的错误计数，以及用于刷新其中错误计数等于或大于阈值的监视块中的数据。

公开(公告)号：US20100037011A1

公开(公告)日：2010-02-11

申请号：US12552442

申请日：2009-09-02

申请人： Hirokuni Yano ,  Shinichi Kanno ,  Toshikatsu Hida ,  Hidenori Matsuzaki ,  Kazuya Kitsunai ,  Shigehiro Asano

发明人： Hirokuni Yano ,  Shinichi Kanno ,  Toshikatsu Hida ,  Hidenori Matsuzaki ,  Kazuya Kitsunai ,  Shigehiro Asano

IPC分类号： G06F12/02

CPC分类号： G06F3/0604 ,  G06F3/0616 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0679 ,  G06F3/0685 ,  G06F12/0246 ,  G06F12/0804 ,  G06F12/0866 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7203 ,  G06F2212/7209 ,  G11C11/5628

摘要： A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second, third, and fourth memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data by a first management unit in the fourth memory area, a third processing for storing data by a second management unit in the third memory area, a fourth processing for moving an area of the third unit having the oldest allocation order in the fourth memory area to the second memory area, and a fifth processing for selecting data in the second memory area and copying the selected data to an empty area of the third unit in the second memory area.

摘要翻译： 半导体存储装置包括配置在非易失性半导体存储器中的易失性半导体存储器，第二，第三和第四存储区域中的第一存储区域和执行以下处理的控制器。 控制器执行第一处理，用于将第一单元存储在第一存储区域中的多个数据，第二处理，用于由第一管理单元存储在第四存储区域中的数据;第三处理，用于由第二管理单元存储数据 在第三存储区域中，用于将第四存储区域中具有最早分配顺序的第三单元的区域移动到第二存储区域的第四处理，以及用于选择第二存储区域中的数据并复制所选数据的第五处理 到第二存储器区域中的第三单元的空区域。

公开(公告)号：US20080120467A1

公开(公告)日：2008-05-22

申请号：US11878019

申请日：2007-07-20

申请人： Shigehiro Asano

发明人： Shigehiro Asano

IPC分类号： G06F12/08

CPC分类号： G06F12/0811 ,  G06F12/0864 ,  Y02D10/13

摘要： An information processing apparatus includes: a main memory that stores data; a plurality of processors each provided with a primary cache memory; a secondary cache memory that is provided between the main memory and the processors, the secondary cache memory having larger capacity than the primary cache memory; and a cache controller that performs cache search on the secondary cache memory based on a second index uniquely generated by joining: 1) a bit string having a predetermined bit length; and 2) a first index that is included in a data access command transmitted from any one of the processors, the first index being used for performing cache search on the primary cache memory.

摘要翻译： 信息处理装置包括：存储数据的主存储器; 多个处理器，每个处理器都具有主高速缓冲存储器; 提供在主存储器和处理器之间的二级高速缓冲存储器，二次高速缓冲存储器具有比主高速缓存存储器大的容量; 以及高速缓存控制器，其基于通过以下方式唯一地生成的第二索引来对二次高速缓冲存储器执行高速缓存搜索：1）具有预定位长度的位串; 以及2）包括在从任一个处理器发送的数据访问命令中的第一索引，第一索引被用于在主缓存存储器上执行高速缓存搜索。

公开(公告)号：US20070283100A1

公开(公告)日：2007-12-06

申请号：US11635518

申请日：2006-12-08

申请人： Shigehiro Asano ,  Takashi Yoshikawa

发明人： Shigehiro Asano ,  Takashi Yoshikawa

IPC分类号： G06F12/00

CPC分类号： G06F12/084 ,  Y02D10/13

摘要： A cache memory device includes a command receiving unit that receives a plurality of commands from each of a plurality of processors; a processing unit that performs a process based on each of the commands; and a storage unit that stores in a queue a first command, when the command receiving unit receives the first command while the processing unit is processing a second command, a cache line address corresponding to the first command being identical to the cache line address corresponding to the second command which is being processed by the processing unit.

摘要翻译： 高速缓冲存储器装置包括从多个处理器中的每一个接收多个命令的命令接收单元; 处理单元，其基于每个命令执行处理; 以及存储单元，其在队列中存储第一命令，当所述命令接收单元在所述处理单元处理第二命令时接收到所述第一命令时，对应于所述第一命令的高速缓存行地址与对应于所述第一命令的高速缓存行地址相同 由处理单元处理的第二命令。

公开(公告)号：US07290074B2

公开(公告)日：2007-10-30

申请号：US11100081

申请日：2005-04-06

申请人： Shigehiro Asano ,  Tsutomu Ishli

发明人： Shigehiro Asano ,  Tsutomu Ishli

IPC分类号： G06F13/00

CPC分类号： G06F13/4009

摘要： Systems and methods for implementing back-off timing for retries of commands sent from a master device to a slave device over a split-transaction bus. One embodiment includes a buffer having entries for storing each pending command and associated information, including a number of retries of the command and a static pseudorandom timer expiration value. The timer expiration value of each entry is compared to a running counter according to a mask associated with the number of retries of the command corresponding to the entry. When the unmasked bits of the two values match, the command is retried. In one embodiment, the same portion of the buffer entry that is used to store the number of retries and the timer expiration value is alternately used to store a slave-generated tag that is received with an acknowledgment response.

摘要翻译： 用于通过分割事务总线实现从主设备发送到从设备的命令重试的退避时序的系统和方法。 一个实施例包括具有用于存储每个未决命令和相关信息的条目的缓冲器，包括命令的重试次数和静态伪随机定时器到期值。 根据与对应于条目的命令的重试次数相关联的掩码，将每个条目的定时器到期值与运行计数器进行比较。 当两个值的未屏蔽位匹配时，将重试该命令。 在一个实施例中，用于存储重试次数和定时器到期值的缓冲器条目的相同部分交替地用于存储用确认响应接收的从生产标签。

公开(公告)号：US20070078120A1

公开(公告)日：2007-04-05

申请号：US10576581

申请日：2004-10-19

申请人： Hitoshi Ban ,  Satoshi Ohnuma ,  Norie Tsuboya ,  Shigehiro Asano

发明人： Hitoshi Ban ,  Satoshi Ohnuma ,  Norie Tsuboya ,  Shigehiro Asano

IPC分类号： A61K31/4439 ,  A61K31/4545 ,  A61K31/397

CPC分类号： C07D295/155 ,  C07C309/46 ,  C07C311/21 ,  C07C317/36 ,  C07C323/36 ,  C07C2601/14 ,  C07D211/22 ,  C07D211/26 ,  C07D211/64 ,  C07D223/04 ,  C07D223/06 ,  C07D401/12

摘要： The invention provides a compound of the following formula (1): wherein m, n, and p are independently an integer of 0-4, provided 3≦m+n≦8; X is nitrogen atom or a group of the formula: C—R15; Y is a substituted or unsubstituted aromatic group, etc.; R15, R1, R2, R3, R4, R5, R6 and R7 are hydrogen atom, a substituted or unsubstituted alkyl group, etc.; and Z is hydrogen atom, cyano group, etc., or a prodrug thereof, or a pharmaceutically acceptable salt thereof, which exhibits an action for enhancing LDL receptor expression, and is useful as a medicament for treating hyperlipidemia, atherosclerosis, etc.

摘要翻译： 本发明提供下式（1）的化合物：其中m，n和p独立地为0-4的整数，条件是3 <= m + n <= 8; X是氮原子或下式的基团：C-R 15; Y是取代或未取代的芳基等; R 15，R 1，R 2，R 3，R 4， R 5，R 6和R 7是氢原子，取代或未取代的烷基等; Z为氢原子，氰基等，或其前体药物或其药学上可接受的盐，其具有增强LDL受体表达的作用，可用作治疗高脂血症，动脉粥样硬化等的药物。

公开(公告)号：US20060236008A1

公开(公告)日：2006-10-19

申请号：US11106791

申请日：2005-04-15

申请人： Shigehiro Asano ,  Tsutomu Ishii

发明人： Shigehiro Asano ,  Tsutomu Ishii

IPC分类号： G06F13/00

CPC分类号： G06F13/42

摘要： Systems and methods for facilitating the location of entries in a buffer where a slave device stores information related to an active transaction so that the entries can be removed if the corresponding transactions are canceled. In one embodiment, multiple master devices and multiple slave devices are coupled to a split transaction bus. When a read command is received by a target slave device, the slave device generates an acknowledgment if the slave's command buffer has available entries, or a retry reply if the slave's command buffer is full. The acknowledgment includes a tag which is an index to the buffer location in which the command is stored. If a combined response to the command which is received by the slave device is a retry, the tag, which is included therein, is used by the slave to clear the command from its command buffer.

摘要翻译： 用于促进在缓冲器中的条目的位置的系统和方法，其中从设备存储与活动事务相关的信息，使得如果对应的事务被取消，则可以移除条目。 在一个实施例中，多个主设备和多个从设备耦合到分离事务总线。 当目标从设备接收到读命令时，如果从站的命令缓冲区有可用条目，则从站设备生成一个确认，或者如果从站的命令缓冲区已满，则重试应答。 该确认包括作为其中存储命令的缓冲器位置的索引的标签。 如果对由从设备接收到的命令的组合响应是重试，则被包括在其中的标签被从机用来从其命令缓冲器中清除该命令。

公开(公告)号：US20060190647A1

公开(公告)日：2006-08-24

申请号：US11063174

申请日：2005-02-22

申请人： Shigehiro Asano ,  Tsutomu Ishii

发明人： Shigehiro Asano ,  Tsutomu Ishii

IPC分类号： G06F13/00

CPC分类号： G06F13/4221

摘要： Systems and methods for enabling a slave device to generate a tag that is an index into a buffer where the slave device stores information related to an active transaction such as a write command received by a master device. The tag is sent to the master device with a reply (such as a response to a write command received from the master device), the master device returns the tag with the data to be written to the slave device. The slave device can efficiently associate the received data with the previously sent write command by retrieving the command from the buffer using the tag as an index into the buffer. Additional hardware such as a content-addressable memory unit is not required to make the association.

摘要翻译： 用于使从设备能够生成作为缓存器的索引的标签的系统和方法，其中从设备存储与主设备接收的诸如写命令之类的活动事务相关的信息。 标签通过回复（例如对从主设备接收到的写命令的响应）发送到主设备，主设备将具有要写入从设备的数据的标签返回。 从设备可以通过使用标签作为缓冲器的索引从缓冲器中检索命令来有效地将接收到的数据与先前发送的写入命令相关联。 不需要诸如内容寻址存储器单元的附加硬件来进行关联。