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71.发明申请公开(公告)号：US20110111752A1
公开(公告)日：2011-05-12
申请号：US12614271
申请日：2009-11-06
IPC分类号： H04W24/00
CPC分类号： H04W24/08 , Y02D70/1242 , Y02D70/1262 , Y02D70/142 , Y02D70/144 , Y02D70/146 , Y02D70/22
摘要： A method and apparatus evaluating base station efficiency in a network. The method may comprises: obtaining, from a plurality of base stations, cell performance measurements, wherein the cell performance measurements include a transmitted carrier power value and a dedicated channel (DCH) power value, generating a plurality of cell efficiency coefficients for each of the plurality of base stations by processing the obtained cell performance measurements, determining if at least one of the plurality of base stations is an inefficient base station from at least one of the plurality of cell efficiency coefficients, and transmitting at least one network modification suggestion, wherein the at least one network modification suggestion is based on the at least one of the plurality of cell efficiency coefficients used in determining the at least one inefficient base station.
摘要翻译： 评估网络中基站效率的方法和装置。 该方法可以包括：从多个基站获得小区性能测量，其中小区性能测量包括传输的载波功率值和专用信道（DCH）功率值，产生多个小区效率系数 多个基站，通过处理所获得的小区性能测量，确定所述多个基站中的至少一个基站是否是所述多个小区效率系数中的至少一个的低效基站，以及发送至少一个网络修改建议，其中， 所述至少一个网络修改建议基于用于确定所述至少一个低效率基站中的所述多个小区效率系数中的至少一个。
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72.发明申请Contemporaneous margin verification and memory access fr memory cells in cross point memory arrays 有权交叉点存储器阵列中的同时保证金验证和存储器访问fr存储器单元公开(公告)号：US20100073990A1
公开(公告)日：2010-03-25
申请号：US12284227
申请日：2008-09-19
CPC分类号： G11C13/0069 , G11C11/5685 , G11C13/0007 , G11C13/0033 , G11C13/004 , G11C13/0061 , G11C16/3418 , G11C16/3431 , G11C2013/0054 , G11C2211/5634 , G11C2211/5646 , G11C2213/71 , G11C2213/77
摘要： Circuitry and methods for restoring data values in non-volatile memory are disclosed. An integrated circuit includes a memory access circuit and a sensing circuit configured to sense a data signal during a read operation to at least one two-terminal non-volatile cross-point memory array. Each memory array includes a plurality of two-terminal memory cells. A plurality of the memory arrays can be fabricated over the substrate and vertically stacked on one another. Further, the integrated circuit can include a margin manager circuit configured to manage a read margin for the two-terminal memory cells substantially during the read operation, thereby providing for contemporaneous read and margin determination operations. Stored data read from the two-terminal memory cells may have a value of the stored data restored (e.g., re-written to the same cell or another cell) if the value is not associated with a read margin (e.g., a hard programmed or hard erased state).
摘要翻译： 公开了用于恢复非易失性存储器中的数据值的电路和方法。 集成电路包括存储器访问电路和被配置为在至少一个两端非易失性交叉点存储器阵列的读取操作期间感测数据信号的感测电路。 每个存储器阵列包括多个两端存储单元。 可以在衬底上制造多个存储器阵列并且彼此垂直地堆叠。 此外，集成电路可以包括边缘管理器电路，其被配置为基本上在读取操作期间管理两端存储器单元的读取余量，从而提供同时的读取和余量确定操作。 从两端存储单元读取的存储数据可以具有恢复的存储数据的值（例如，重新写入同一单元或另一单元），如果该值不与读取余量相关联（例如，硬编程或 硬擦除状态）。
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公开(公告)号：US07428714B2
公开(公告)日：2008-09-23
申请号：US10781959
申请日：2004-02-19
CPC分类号： G06F17/5081
摘要： A method of checking for errors in line width in an integrated circuit includes identifying with a marker any lines having a line width greater than a minimum line width, and associating a line width parameter with each line width marker, the line width parameter corresponding to a line width for the marked line. The line width parameters for each line width marker are compared to the actual layout line width.
摘要翻译： 一种在集成电路中检查线宽中的误差的方法包括用标记识别具有大于最小线宽的线宽的线，以及将线宽参数与每个线宽标记相关联，线宽度参数对应于 标记线的线宽。 将每个线宽标记的线宽参数与实际布局线宽进行比较。
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公开(公告)号：US20070008783A1
公开(公告)日：2007-01-11
申请号：US11519679
申请日：2006-09-12
CPC分类号： G11C16/3404 , G11C16/344
摘要： A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to bit lines. A verify circuit is coupled to the bit lines to determine if memory cells have a erase level that is within predetermined upper and lower limits. The verify circuit can include first and second comparators. In one embodiment, the first comparator is used to compare a bit line current with an upper first reference current. The second comparator is used to compare a bit line current with a lower second reference current. The comparator circuit is not limited to reference currents, but can use reference voltages to compare to a bit line voltage. The verify circuit, therefore, eliminates the need for separate bit line leakage testing to identify over-erased memory cells.
摘要翻译： 存储器件验证系统确定存储器中存储器单元的状态。 存储器包括具有耦合到位线的多个存储器单元的存储器阵列。 验证电路耦合到位线以确定存储器单元是否具有在预定的上限和下限内的擦除电平。 验证电路可以包括第一和第二比较器。 在一个实施例中，第一比较器用于将位线电流与较高的第一参考电流进行比较。 第二比较器用于将位线电流与较低的第二参考电流进行比较。 比较器电路不限于参考电流，但可以使用参考电压与位线电压进行比较。 因此，验证电路不需要单独的位线泄漏测试来识别过度擦除的存储器单元。
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公开(公告)号：US07155589B2
公开(公告)日：2006-12-26
申请号：US11199321
申请日：2005-08-08
IPC分类号： G06F12/00
CPC分类号： G06F12/1433 , G06F2212/2022
摘要： A secure command is entered into a Flash memory device. A control data word is written to the memory device to specify which blocks of memory are to be permanently secured against write and erase operations. The bits of the control data word specify different blocks of memory to be permanently secured.
摘要翻译： 闪存设备中输入安全命令。 将控制数据字写入存储器设备，以指定要对写入和擦除操作永久地保护哪些存储器块。 控制数据字的位指定要永久保护的不同的存储块。
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公开(公告)号：US20060181930A1
公开(公告)日：2006-08-17
申请号：US11400993
申请日：2006-04-10
IPC分类号： G11C11/34
CPC分类号： G11C16/3404 , G11C16/344
摘要： A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to bit lines. A verify circuit is coupled to the bit lines to determine if memory cells have a erase level that is within predetermined upper and lower limits. The verify circuit can include first and second comparators. In one embodiment, the first comparator is used to compare a bit line current with an upper first reference current. The second comparator is used to compare a bit line current with a lower second reference current. The comparator circuit is not limited to reference currents, but can use reference voltages to compare to a bit line voltage. The verify circuit, therefore, eliminates the need for separate bit line leakage testing to identify over-erased memory cells.
摘要翻译： 存储器件验证系统确定存储器中存储器单元的状态。 存储器包括具有耦合到位线的多个存储器单元的存储器阵列。 验证电路耦合到位线以确定存储器单元是否具有在预定的上限和下限内的擦除电平。 验证电路可以包括第一和第二比较器。 在一个实施例中，第一比较器用于比较位线电流和较高的第一参考电流。 第二比较器用于将位线电流与较低的第二参考电流进行比较。 比较器电路不限于参考电流，但可以使用参考电压与位线电压进行比较。 因此，验证电路不需要单独的位线泄漏测试来识别过度擦除的存储器单元。
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公开(公告)号：US07032199B2
公开(公告)日：2006-04-18
申请号：US10781964
申请日：2004-02-19
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method of design rule checking an integrated circuit identifies any line having a line width marker and line width parameter, extracts each line having a line width marker, determines the line width parameter for each extracted line, and compares the line width parameter with an actual line width for the line.
摘要翻译： 设计规则检查集成电路的方法识别具有线宽标记和线宽参数的任何线，提取具有线宽标记的每条线，确定每条提取线的线宽参数，并将线宽参数与实际 线宽线。
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公开(公告)号：US20050270839A1
公开(公告)日：2005-12-08
申请号：US11198212
申请日：2005-08-05
CPC分类号： G11C16/3404 , G11C16/344
摘要： A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to bit lines. A verify circuit is coupled to the bit lines to determine if memory cells have a erase level that is within predetermined upper and lower limits. The verify circuit can include first and second comparators. In one embodiment, the first comparator is used to compare a bit line current with an upper first reference current. The second comparator is used to compare a bit line current with a lower second reference current. The comparator circuit is not limited to reference currents, but can use reference voltages to compare to a bit line voltage. The verify circuit, therefore, eliminates the need for separate bit line leakage testing to identify over-erased memory cells.
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公开(公告)号：US06940780B2
公开(公告)日：2005-09-06
申请号：US10784688
申请日：2004-02-23
IPC分类号： G11C7/18 , G11C29/02 , H01L27/115 , H01L11/401
CPC分类号： G11C29/025 , G11C7/18 , G11C29/02 , H01L27/115
摘要： A flash memory device that can detect short circuits in local and global bit lines. The flash memory device has a plurality of sets of adjacent local bit lines, a plurality of global bit lines and a plurality of select transistors. Each select transistor has a control gate and is coupled between one of the local bit lines in each set of local bit lines and one of the global bit lines. Thus, each local bit line in each set of local bit lines is coupled to a different global bit line. Multiple select lines are used to activate the control gates on the select transistors. Each select line is coupled to the control gates on associated select transistors. The associated select transistors are select transistors that are coupled to the local bit lines in an associated set of local bit lines.
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80.发明申请Segmented non-volatile memory array with multiple sources having improved source line decode circuitry 审中-公开具有多个源的分段非易失性存储器阵列具有改进的源极线解码电路公开(公告)号：US20050190638A1
公开(公告)日：2005-09-01
申请号：US11103988
申请日：2005-04-12
IPC分类号： G11C16/08 , H01L27/115 , G11C16/04
CPC分类号： H01L27/115 , G11C16/08
摘要： A flash memory array arrangement having a plurality of erase blocks which can be separately erased. The erase blocks have separate source lines, the state of which is controlled by a source line decoder. In array read, program and erase operations, the source lines of the deselected erase blocks, the blocks that are not being read, programmed or erased, are set to a high impedance level. If a cell in one of the deselected erase blocks is defective in some respect such that the cell is conducting leakage current, the high impedance source line associated with the cell will reduce the likelihood that the defective cell will prevent proper operation of the selected erase block.
摘要翻译： 一种闪存阵列装置，具有可以单独擦除的多个擦除块。 擦除块具有分离的源极线，其状态由源极线解码器控制。 在阵列读取，编程和擦除操作中，未选择的擦除块的源线，未被读取，编程或擦除的块被设置为高阻抗级。 如果一个取消选择的擦除块中的单元在某些方面是有缺陷的，使得单元导致漏电流，则与单元相关联的高阻抗源极线将降低有缺陷单元将阻止所选擦除块的正确操作的可能性 。
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