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77 条记录 (耗时 0.081 秒)

    Hybrid phase/delay locked loop circuits and methods
    71.
    发明授权
    Hybrid phase/delay locked loop circuits and methods 失效
    混合相位/延迟锁定环路电路及方法

    公开(公告)号：US06995590B1

    公开(公告)日：2006-02-07

    申请号：US10668447

    申请日：2003-09-22

    申请人： Bruce Pedersen

    发明人： Bruce Pedersen

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0812 ,  H03L7/083 ,  H03L7/0995 ,  H03L7/18

    摘要： A circuit is provided that aligns the phase of a delay signal with an input clock signal. The circuit functions as a phase locked loop (PLL) in a first state of operation and as a delay locked loop (DLL) in a second state of operation. An adjustable delay circuit generates the delay signal. A phase detector compares the input clock signal to the delay signal to generate a phase detection signal. The adjustable delay circuit adjusts the phase of the delay signal in response to the phase detection signal. A multiplexer couples the delay signal back to the input of the adjustable delay circuit using a feedback loop in the first state of operation. The multiplexer couples the input clock signal to the input of the adjustable delay circuit in the second state of operation.

    摘要翻译： 提供了将延迟信号的相位与输入时钟信号对准的电路。 该电路作为处于第一操作状态的锁相环（PLL）和在第二操作状态下作为延迟锁定环（DLL）起作用。 可调延迟电路产生延迟信号。 相位检测器将输入时钟信号与延迟信号进行比较以产生相位检测信号。 可调节延迟电路根据相位检测信号调整延迟信号的相位。 多路复用器使用第一操作状态的反馈回路将延迟信号耦合回可调节延迟电路的输入端。 在第二操作状态下，多路复用器将输入时钟信号耦合到可调延迟电路的输入。

    Fracturable incomplete look up table for area efficient logic elements
    74.
    发明授权
    Fracturable incomplete look up table for area efficient logic elements 有权
    用于区域高效逻辑元素的难以置信的不完整查询表

    公开(公告)号：US06888373B2

    公开(公告)日：2005-05-03

    申请号：US10365647

    申请日：2003-02-11

    申请人： Sinan Kaptanoglu ,  David Lewis ,  Bruce Pedersen

    发明人： Sinan Kaptanoglu ,  David Lewis ,  Bruce Pedersen

    IPC分类号： H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/17748 ,  H03K19/17728

    摘要： Disclosed is a configurable logic circuit that includes at least 6 inputs and at least two outputs. The configurable logic element can carry out only a subset of all 6-input logic functions and, thus, requires a substantially smaller silicon area than a 6-LUT that can perform all 6-input logic functions. Also, the configurable logic circuit can be configured such that a first subset of the inputs drive one of the outputs and a second subset of the inputs drive another output.

    摘要翻译： 公开了一种可配置逻辑电路，其包括至少6个输入和至少两个输出。 可配置逻辑元件只能执行所有6输入逻辑功能的一个子集，因此需要比可执行所有6输入逻辑功能的6-LUT更小的硅面积。 而且，可配置逻辑电路可被配置为使得输入的第一子集驱动输出之一，并且输入的第二子集驱动另一输出。

    Interconnection resources for programmable logic integrated circuit devices
    76.
    发明授权
    Interconnection resources for programmable logic integrated circuit devices 有权
    可编程逻辑集成电路器件的互连资源

    公开(公告)号：US06366120B1

    公开(公告)日：2002-04-02

    申请号：US09517146

    申请日：2000-03-02

    申请人： James Schleicher ,  James Park ,  Sergey Shumarayev ,  Bruce Pedersen ,  Tony Ngai ,  Wei-Jen Huang ,  Victor Maruri ,  Rakesh Patel

    发明人： James Schleicher ,  James Park ,  Sergey Shumarayev ,  Bruce Pedersen ,  Tony Ngai ,  Wei-Jen Huang ,  Victor Maruri ,  Rakesh Patel

    IPC分类号： H03K190177

    CPC分类号： G06F7/506 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17792

    摘要： A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

    摘要翻译： 可编程逻辑器件具有许多可编程逻辑区域，以及可用于在几乎任何逻辑区域之间进行互连的相对通用的，可编程的互连资源。 此外，各种类型的更多本地互连资源与每个逻辑区域相关联，以便于在相邻或附近的逻辑区域之间建立互连，而不需要使用这些互连的通用互连资源。 本地互连资源通过相对直接的和因此的高速互连来支持逻辑区域的灵活聚集，优选地在逻辑区域的典型二维阵列中的水平和垂直方向。 由本地互连资源提供的逻辑区域聚类选项优选地在逻辑区域阵列内是无边界的或基本无边界的。

    Apparatus and method for centralized generation of an enabled clock signal for a logic array block of a programmable logic device
    77.
    发明授权
    Apparatus and method for centralized generation of an enabled clock signal for a logic array block of a programmable logic device 失效
    用于集中生成用于可编程逻辑器件的逻辑阵列块的使能时钟信号的装置和方法

    公开(公告)号：US06249149B1

    公开(公告)日：2001-06-19

    申请号：US09012682

    申请日：1998-01-23

    申请人： Bruce Pedersen

    发明人： Bruce Pedersen

    IPC分类号： H03K1900

    CPC分类号： G06F1/10

    摘要： A logic array block of a programmable logic device includes a clock generation circuit. The clock generation circuit has an input node to receive a clock signal, an enable signal input node to receive an enable signal, a clock generation circuit output node, and a digital logic circuit connected between the clock generation circuit input node, the enable signal input node, and the clock generation circuit output node. The digital logic circuit generates an enabled clock signal on the clock generation circuit output node in response to the clock signal and the enable signal when the enable signal has been asserted during a previous clock state of the clock signal. A set of logic elements, each of which includes a logic element clock input node, is connected to the clock generation circuit output node such that each logic element of the set of logic elements receives the enabled clock signal from the clock generation circuit.

    摘要翻译： 可编程逻辑器件的逻辑阵列块包括时钟产生电路。 时钟发生电路具有接收时钟信号的输入节点，接收使能信号的使能信号输入节点，时钟产生电路输出节点和连接在时钟发生电路输入节点之间的数字逻辑电路，使能信号输入 节点和时钟生成电路输出节点。 数字逻辑电路响应于时钟信号和使能信号在时钟信号的先前时钟状态中被使能信号被置位而在时钟产生电路输出节点上产生使能的时钟信号。 一组逻辑元件，每个逻辑元件包括逻辑元件时钟输入节点，连接到时钟产生电路输出节点，使得该组逻辑元件的每个逻辑元件从时钟产生电路接收使能的时钟信号。