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公开(公告)号:US07755923B2
公开(公告)日:2010-07-13
申请号:US12212798
申请日:2008-09-18
申请人: Hongyue Liu , Yong Lu , Andrew Carter , Yiran Chen , Hai Li
发明人: Hongyue Liu , Yong Lu , Andrew Carter , Yiran Chen , Hai Li
IPC分类号: G11C11/00
CPC分类号: G11C7/14 , G11C11/1673
摘要: The present disclosure relates to memory arrays with read reference voltage cells. In particular the present disclosure relates to variable resistive memory cell apparatus and arrays that include a high resistance state reference memory cell and a low resistance state reference memory cell that provides a reliable average reference voltage on chip to compare to a read voltage of a selected memory cell and determine if the selected memory cell is in the high resistance state or low resistance state. These memory arrays are particularly suitable for use with spin-transfer torque memory cells and resolves many systematic issues related to generation of a reliable reference voltage.
摘要翻译: 本公开涉及具有读取参考电压单元的存储器阵列。 特别地,本公开涉及包括高电阻状态参考存储单元和低电阻状态参考存储单元的可变电阻存储单元设备和阵列,其提供片上可靠的平均参考电压以与所选择的存储器的读取电压进行比较 并确定所选存储单元是处于高电阻状态还是低电阻状态。 这些存储器阵列特别适用于自旋转移转矩存储单元,并且解决了与生成可靠参考电压有关的许多系统问题。
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公开(公告)号:US20100174766A1
公开(公告)日:2010-07-08
申请号:US12349354
申请日:2009-01-06
申请人: Thomas Weeks , Yong Lu , Xiaobin Wang
发明人: Thomas Weeks , Yong Lu , Xiaobin Wang
IPC分类号: G06F7/58
摘要: A method and apparatus for generating a random logic bit value. In some embodiments, a spin polarized current is created by flowing a pulse current through a spin polarizing material. The spin polarized current is injected in a free layer of a magnetic tunneling junction and a random logical bit value results from a variation in pulse current duration or a variation in thermal properties.
摘要翻译: 一种用于产生随机逻辑比特值的方法和装置。 在一些实施例中,通过使脉冲电流流过自旋极化材料产生自旋极化电流。 自旋极化电流被注入到磁隧道结的自由层中,随机逻辑位值由脉冲电流持续时间的变化或热性质的变化产生。
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73.
公开(公告)号:US20100118587A1
公开(公告)日:2010-05-13
申请号:US12269564
申请日:2008-11-12
申请人: Yiran Chen , Daniel S. Reed , Yong Lu , Harry Hongyue Liu , Hai Li
发明人: Yiran Chen , Daniel S. Reed , Yong Lu , Harry Hongyue Liu , Hai Li
IPC分类号: G11C11/00 , G11C8/00 , G11C11/416
CPC分类号: G11C8/12 , G11C11/1653 , G11C11/1673 , G11C11/1675 , G11C13/0007 , G11C13/0069 , G11C2013/0088 , G11C2013/009 , G11C2213/32 , G11C2213/34 , G11C2213/79
摘要: Various embodiments of the present invention are generally directed to a method and apparatus for carrying out a partial block update operation upon a resistive sense memory (RSM) array, such as formed from STRAM or RRAM cells. The RSM array is arranged into multi-cell blocks (sectors), each block having a physical block address (PBA). A first set of user data is written to a selected block at a first PBA. A partial block update operation is performed by writing a second set of user data to a second block at a second PBA, the second set of user data updating a portion of the first set of user data in the first PBA. The first and second blocks are thereafter read to retrieve the second set of user data and a remaining portion of the first set of user data.
摘要翻译: 本发明的各种实施例总体上涉及一种用于在诸如由STRAM或RRAM单元形成的电阻式感测存储器(RSM)阵列上执行部分块更新操作的方法和装置。 RSM阵列被布置成多小区块(扇区),每个块具有物理块地址(PBA)。 第一组用户数据在第一PBA被写入所选择的块。 通过在第二PBA将第二组用户数据写入第二块来执行部分块更新操作,第二组用户数据更新第一PBA中第一组用户数据的一部分。 然后读取第一和第二块以检索第二组用户数据和第一组用户数据的剩余部分。
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公开(公告)号:US20100091562A1
公开(公告)日:2010-04-15
申请号:US12250036
申请日:2008-10-13
申请人: Yiran Chen , Hai Li , Hongyue Liu , Henry F. Huang , Yong Lu
发明人: Yiran Chen , Hai Li , Hongyue Liu , Henry F. Huang , Yong Lu
CPC分类号: G11C7/04 , G11C11/1659 , G11C11/1673
摘要: A memory device that includes at least one memory cell, the memory cell includes: a magnetic tunnel junction (MTJ); and a transistor, wherein the transistor is operatively coupled to the MTJ; a bit line; a source line; and a word line, wherein the memory cell is operatively coupled between the bit line and the source line, and the word line is operatively coupled to the transistor; a temperature sensor; and control circuitry, wherein the temperature sensor is operatively coupled to the control circuitry and the control circuitry and temperature sensor are configured to control a current across the memory cell.
摘要翻译: 一种包括至少一个存储单元的存储器件,所述存储单元包括:磁性隧道结(MTJ); 和晶体管,其中所述晶体管可操作地耦合到所述MTJ; 有点线 源线; 和字线,其中所述存储器单元可操作地耦合在所述位线和所述源极线之间,并且所述字线可操作地耦合到所述晶体管; 温度传感器; 以及控制电路,其中所述温度传感器可操作地耦合到所述控制电路,并且所述控制电路和温度传感器被配置为控制横跨所述存储器单元的电流。
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公开(公告)号:US20100085795A1
公开(公告)日:2010-04-08
申请号:US12408996
申请日:2009-03-23
申请人: Wenzhong Zhu , Yong Lu , Xiaobin Wang , Yiran Chen , Alan Xuguang Wang , Xiaohua Lou , Haiwen Xi
发明人: Wenzhong Zhu , Yong Lu , Xiaobin Wang , Yiran Chen , Alan Xuguang Wang , Xiaohua Lou , Haiwen Xi
IPC分类号: G11C11/00 , G11C11/14 , G11C11/416
CPC分类号: G11C11/16 , G11C11/1659 , G11C11/1675
摘要: An apparatus and method for compensating for asymmetric write current in a non-volatile unit cell. The unit cell comprises a switching device and an asymmetric resistive sense element (RSE), such as an asymmetric resistive random access memory (RRAM) element or an asymmetric spin-torque transfer random access memory (STRAM) element. The RSE is physically oriented within the unit cell relative to the switching device such that a hard direction for programming the RSE is aligned with an easy direction of programming the unit cell, and an easy direction for programming the RSE is aligned with a hard direction for programming the unit cell.
摘要翻译: 一种用于补偿非易失性单元中不对称写入电流的装置和方法。 单位单元包括开关装置和非对称电阻感测元件(RSE),诸如非对称电阻随机存取存储器(RRAM)元件或非对称自旋转矩传递随机存取存储器(STRAM)元件。 RSE相对于开关装置在物理上定位在单位单元内,使得用于编程RSE的硬方向与单元单元的简单编程方向对齐,并且用于编程RSE的简单方向与硬方向对齐 编程单元格
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公开(公告)号:US20100080071A1
公开(公告)日:2010-04-01
申请号:US12242590
申请日:2008-09-30
申请人: Henry F. Huang , Hai (Helen) Li , Yong Lu
发明人: Henry F. Huang , Hai (Helen) Li , Yong Lu
IPC分类号: G11C11/416
CPC分类号: G11C13/0069 , G11C7/1006 , G11C7/1009 , G11C11/1673 , G11C11/1675 , G11C13/00 , G11C13/0004 , G11C2013/0076
摘要: Method and apparatus for writing data to a storage array, such as but not limited to an STRAM or RRAM memory array, using a read-mask-write operation. In accordance with various embodiments, a first bit pattern stored in a plurality of memory cells is read. A second bit pattern is stored to the plurality of memory cells by applying a mask to selectively write only those cells of said plurality corresponding to different bit values between the first and second bit patterns.
摘要翻译: 使用读取 - 写入操作将数据写入存储阵列(例如但不限于STRAM或RRAM存储器阵列)的方法和装置。 根据各种实施例,读取存储在多个存储单元中的第一位模式。 第二位模式通过施加掩模来存储到多个存储器单元,以仅选择性地仅写入在第一和第二位模式之间对应于不同位值的所述多个存储单元。
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公开(公告)号:US20100067281A1
公开(公告)日:2010-03-18
申请号:US12210526
申请日:2008-09-15
申请人: Haiwen Xi , Hongyue Liu , Xiaobin Wang , Yong Lu , Yiran Chen , Yuankai Zheng , Dimitar V. Dimitrov , Dexin Wang , Hai Li
发明人: Haiwen Xi , Hongyue Liu , Xiaobin Wang , Yong Lu , Yiran Chen , Yuankai Zheng , Dimitar V. Dimitrov , Dexin Wang , Hai Li
CPC分类号: G11C11/16 , G11C13/0007 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0057
摘要: Variable write and read methods for resistance random access memory (RRAM) are disclosed. The methods include initializing a write sequence and verifying the resistance state of the RRAM cell. If a write pulse is needed, then two or more write pulses are applied through the RRAM cell to write the desired data state to the RRAM cell. Each subsequent write pulse has substantially the same or greater write pulse duration. Subsequent write pulses are applied to the RRAM cell until the RRAM cell is in the desired data state or until a predetermined number of write pulses have been applied to the RRAM cell. A read method is also disclosed where subsequent read pulses are applied through the RRAM cell until the read is successful or until a predetermined number of read pulses have been applied to the RRAM cell.
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78.
公开(公告)号:US07672230B2
公开(公告)日:2010-03-02
申请号:US11484249
申请日:2006-07-10
CPC分类号: H04L12/2801 , H04N21/242
摘要: A dynamic channel change technique is disclosed which may be implemented between nodes and a Head End of an access network. Initially a network device may communicate with the Head End via a first downstream channel and a first upstream channel. When the network device receives a dynamic channel change request which includes instructions for the network device to switch to a second downstream channel, the network device may respond by switching from the first downstream channel to the second downstream channel. Thereafter, the network device may communicate with the Head End via the second downstream channel and first upstream channel. Further, according to a specific embodiment, the dynamic channel change request may also include an upstream channel change request for causing the network device to switch from a first upstream channel to a second upstream channel.
摘要翻译: 公开了可以在接入网络的节点和头端之间实现的动态信道改变技术。 最初,网络设备可以经由第一下游信道和第一上行信道与头端进行通信。 当网络设备接收到包括用于网络设备切换到第二下行信道的指令的动态信道改变请求时,网络设备可以通过从第一下游信道切换到第二下游信道来进行响应。 此后,网络设备可以经由第二下游信道和第一上行信道与头端进行通信。 此外,根据具体实施例,动态信道改变请求还可以包括用于使网络设备从第一上行信道切换到第二上行信道的上行信道改变请求。
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公开(公告)号:US07092285B1
公开(公告)日:2006-08-15
申请号:US10992052
申请日:2004-11-18
申请人: Yong Lu , Romney R. Katti
发明人: Yong Lu , Romney R. Katti
IPC分类号: G11C11/00
CPC分类号: G11C5/14 , G11C5/144 , G11C11/16 , Y10T307/527
摘要: The semiconductor industry seeks to reduce the risk of traditional volatile storage devices with improved non-volatile storage devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated giant-magneto-resistive (GMR) structures. The present invention relates to non-volatile logic state retention devices, such as GMR storage elements, and concerns a save-on-power-down circuit that may be integrated with conventional semiconductor-based computing, logic, and memory devices to retain volatile logic states and/or volatile digital information in a non-volatile manner.
摘要翻译: 半导体行业旨在通过改进的非易失性存储设备降低传统易失性存储设备的风险。 对于显着提升,高效和非易失性数据保留技术的需求的增加推动了集成的巨磁阻(GMR)结构的发展。 本发明涉及诸如GMR存储元件的非易失性逻辑状态保持器件,并且涉及可以与常规的基于半导体的计算,逻辑和存储器件集成以保存易失性逻辑的保存在掉电电路 状态和/或易失性数字信息。
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80.
公开(公告)号:US20060143193A1
公开(公告)日:2006-06-29
申请号:US11025323
申请日:2004-12-29
申请人: Jigar Thakkar , Jagan Peri , Andrey Zaytsev , Michaeljon Miller , Navin Thadani , Yong Lu , Jasjit Grewal
发明人: Jigar Thakkar , Jagan Peri , Andrey Zaytsev , Michaeljon Miller , Navin Thadani , Yong Lu , Jasjit Grewal
IPC分类号: G06F17/00
CPC分类号: G06Q10/10 , Y10S707/99944
摘要: A metadata driven system for supporting business application software required in the middle tier for a line of business applications includes a process metadata module adapted to store a process in metadata format, wherein the process object contains logic related to an entity of the application software. The system allows for persistence of various entities like accounts, incidents, etc., and allows an end user of the business application software to create new types of entities. The system also allows the end user to perform critical business logic operations even on the new entities defined by the end user after the deployment of the business application without requiring recompilation of the business application software. The metadata driven approach allows to easily make changes to business applications and to automate quality assurance of objects built on top of the business applications.
摘要翻译: 用于支持业务应用程序行的中间层所需的业务应用软件的元数据驱动系统包括适于以元数据格式存储过程的过程元数据模块,其中过程对象包含与应用软件的实体相关的逻辑。 该系统允许诸如帐户,事件等的各种实体的持久性,并允许业务应用软件的最终用户创建新类型的实体。 该系统还允许最终用户即使在部署业务应用程序之后由最终用户定义的新实体执行关键业务逻辑操作,而不需要重新编译业务应用软件。 元数据驱动的方法允许轻松地更改业务应用程序,并自动化在业务应用程序之上构建的对象的质量保证。
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