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    Efficent column redundancy techniques
    72.
    发明授权
    Efficent column redundancy techniques 有权
    效率柱冗余技术

    公开(公告)号：US07230872B2

    公开(公告)日：2007-06-12

    申请号：US11064218

    申请日：2005-02-23

    Applicant: Gil I. Winograd ,  Esin Terzioglu

    Inventor： Gil I. Winograd ,  Esin Terzioglu

    IPC: G11C29/28

    CPC classification number: G11C29/808 ,  G06F13/4086 ,  G11C7/18 ,  G11C11/41 ,  G11C11/419 ,  G11C29/846 ,  G11C29/848

    Abstract: The present invention relates to a system and method adapted to increase memory cell and memory architecture design yield. The present invention includes memory architecture having a decoder and a multi-bank memory. The decoder is adapted to decode addresses. The multi-bank memory interacts with the decoder, wherein the multi-bank memory includes at least one output data bit adapted to complete a word for a failing bank in the multi-bank memory.

    Abstract translation: 本发明涉及适于增加存储器单元和存储器架构设计产量的系统和方法。 本发明包括具有解码器和多存储体存储器的存储器架构。 解码器适用于解码地址。 所述多存储体存储器与所述解码器交互，其中所述多存储体存储器包括适于完成所述多存储体存储器中的故障库的单词的至少一个输出数据位。

    Integrated circuits with reduced leakage current
    74.
    发明申请
    Integrated circuits with reduced leakage current 有权

    公开(公告)号：US20070040575A1

    公开(公告)日：2007-02-22

    申请号：US11301236

    申请日：2005-12-12

    Applicant: Morteza Afghahi ,  Esin Terzioglu ,  Gil Winograd

    Inventor： Morteza Afghahi ,  Esin Terzioglu ,  Gil Winograd

    IPC: H03K19/003

    CPC classification number: H03K19/0016

    Abstract: In one embodiment, NMOS transistors have their source coupled to a common source node such that the NMOS transistors conduct a leakage current if the common source node is grounded. To reduce this leakage current, the common source node is raised in potential. Similarly, PMOS transistors have their source coupled to a common source node such that the PMOS transistors conduct a leakage current if the common source node is charged to a power supply voltage VDD. To reduce this leakage current, the common source node is lowered in potential.

    Hardware and software programmable fuses for memory repair
    75.
    发明申请
    Hardware and software programmable fuses for memory repair 有权

    公开(公告)号：US20060220680A1

    公开(公告)日：2006-10-05

    申请号：US11447495

    申请日：2006-06-06

    Applicant: Esin Terzioglu ,  Gil Winograd

    Inventor： Esin Terzioglu ,  Gil Winograd

    IPC: H03K19/173

    CPC classification number: G11C29/785 ,  G11C7/06 ,  G11C7/18 ,  G11C29/72 ,  G11C2207/002 ,  G11C2207/005 ,  H01L27/10

    Abstract: The present invention relates to a system and method for increasing the manufacturing yield of a plurality of memory cells used in cell arrays. A programmable fuse, having both hardware and software elements, is used with the plurality of memory cells to indicate that at least one memory cell is unusable and should be shifted out of operation. The software programmable element includes a programmable register adapted to shift in an appropriate value indicating that at least one of the memory cells is flawed. The hardware element includes a fuse gated with the programmable register. Shifting is indicated either by software programmable fuse or hard fuse. Soft fuse registers may be chained together forming a shift register.

    Memory module with hierarchical functionality
    76.
    发明授权
    Memory module with hierarchical functionality 失效

    公开(公告)号：US07082076B2

    公开(公告)日：2006-07-25

    申请号：US11209866

    申请日：2005-08-23

    Applicant: Esin Terzioglu ,  Morteza Cyrus Afghahi ,  Mehdi Hatamian

    Inventor： Esin Terzioglu ,  Morteza Cyrus Afghahi ,  Mehdi Hatamian

    IPC: G11C8/10

    CPC classification number: G11C7/06

    Abstract: A hierarchical memory structure having memory cells, and sense amplifiers and decoders coupled with the memory cells to form first tier memory module, and subsequent tiers being formed by having (n−1)-tier memory modules, which are coupled with (n)-tier sense amplifiers and (n)-tier decoders. Also provided are a single-ended sense amplifier having sample-and-hold reference, and a charge-share limited-swing-driver sense amplifier; an asynchronously-resettable decoder; a wordline decoder having row redundancy; a redundancy device having redundant memory cells operated by a redundancy controller; a diffusion replica delay circuit; a high-precision delay measurement circuit; and a data transfer bus circuit imposing a limited voltage swing on a data bus. Methods are provided for a write-after-read operation without an interposed precharge cycle, and write-after-write operation with an interposed precharge cycle are provided, either operation being completed in less than one memory access cycle.

    Sense amplifier with adaptive reference generation
    77.
    发明授权
    Sense amplifier with adaptive reference generation 有权
    具有自适应参考产生的感应放大器

    公开(公告)号：US07054212B2

    公开(公告)日：2006-05-30

    申请号：US11042006

    申请日：2005-01-25

    Applicant: Esin Terzioglu ,  Morteza Cyrus Afghahi ,  Gil I. Winograd

    Inventor： Esin Terzioglu ,  Morteza Cyrus Afghahi ,  Gil I. Winograd

    IPC: G11C7/00

    CPC classification number: G11C7/065 ,  G11C7/14

    Abstract: A digital memory system (30) includes a memory cell (52), a bit line (50), a transfer gate (60) a reference voltage generator (40), a sense amplifier (70) and a control circuit (80). The control circuit precharges the bit line to a bit line precharge voltage, which is sampled and stored. A corresponding reference voltage is generated after the bit line is isolated. The bit line and reference voltage are coupled to the sense amplifier so that a voltage is received based on charge stored in the memory cell. The sense amplifier then is isolated from the bit line and reference voltage and the sense amplifier is energized so that an output voltage is derived from the charge and reference voltage.

    Abstract translation: 数字存储器系统（30）包括存储单元（52），位线（50），转移门（60），参考电压发生器（40），读出放大器（70）和控制电路（80）。 控制电路将位线预充电到采样和存储的位线预充电电压。 在位线隔离之后产生相应的参考电压。 位线和参考电压被耦合到读出放大器，使得基于存储在存储单元中的电荷接收电压。 然后，读出放大器与位线和参考电压隔离，并且读出放大器通电，从而从电荷和参考电压导出输出电压。

    Active pixel array with matching analog-to-digital converters for image processing
    78.
    发明申请
    Active pixel array with matching analog-to-digital converters for image processing 有权
    具有匹配模数转换器的有源像素阵列用于图像处理

    公开(公告)号：US20060049438A1

    公开(公告)日：2006-03-09

    申请号：US11203285

    申请日：2005-08-15

    Applicant: Esin Terzioglu

    Inventor： Esin Terzioglu

    IPC: H01L31/113

    CPC classification number: H04N5/243 ,  H04N5/23245 ,  H04N5/235

    Abstract: An imaging device includes a plurality of photo-diodes arranged in a plurality of columns on a single Complementary Metal Oxide Semiconductor (CMOS) substrate. A plurality of analog-to-digital converters (ADCs) corresponding to the plurality of columns of photo-diodes are arranged on the substrate, with each ADC having an input coupled to outputs of the photo-diodes in the corresponding column. Parallel processing of the data streams produced by the multiple ADCs improves the bandwidth of the imaging device. The ADCs have one or more capacitors based on a reference capacitor that are configured so that the corresponding capacitors for different ADCs are substantially equal across the CMOS substrate. As such, image variation and streaking across the columns of photo-diodes is minimized or eliminated. The reference capacitors of the ADCs are above a minimum capacitance value, determined by a maximum variation of the reference capacitors across the substrate.

    Abstract translation: 成像装置包括在单个互补金属氧化物半导体（CMOS）基板上以多列布置的多个光电二极管。 对应于多列光电二极管的多个模数转换器（ADC）布置在衬底上，每个ADC具有耦合到相应列中的光电二极管的输出的输入。 由多个ADC产生的数据流的并行处理提高了成像设备的带宽。 ADC具有基于参考电容器的一个或多个电容器，其被配置为使得用于不同ADC的相应电容器在CMOS衬底上基本相等。 因此，光电二极管列的图像变化和条纹被最小化或消除。 ADC的参考电容器高于最小电容值，由基板上的参考电容器的最大变化量决定。

    Operational amplifier for an active pixel sensor
    80.
    发明申请
    Operational amplifier for an active pixel sensor 失效

    公开(公告)号：US20060033007A1

    公开(公告)日：2006-02-16

    申请号：US11192372

    申请日：2005-07-29

    Applicant: Esin Terzioglu

    Inventor： Esin Terzioglu

    IPC: H01L27/00

    CPC classification number: H04N5/361 ,  H04N5/235 ,  H04N5/243

    Abstract: The present invention includes operational amplifier for an active pixel sensor that detects optical energy and generates an analog output that is proportional to the optical energy. The active pixel sensor operates in a number of different modes including: signal integration mode, the reset integration mode, column reset mode, and column signal readout mode. Each mode causes the operational amplifier to see a different output load. Accordingly, the operational amplifier includes a variable feedback circuit to provide compensation that provides sufficient amplifier stability for each operating mode of the active pixel sensor. For instance, the operational amplifier includes a bank of feedback capacitors, one or more of which are selected based on the operating mode to provide sufficient phase margin for stability, but also considering gain and bandwidth requirements of the operating mode.

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