公开(公告)号：US10832944B2

公开(公告)日：2020-11-10

申请号：US16177854

申请日：2018-11-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nicholas V. LiCausi ,  Chanro Park ,  Ruilong Xie ,  Andre P. Labonte

IPC: H01L21/768

Abstract: An interconnect structure of an integrated circuit and a method of forming the same, the interconnect structure including: at least two metal lines laterally spaced from one another in a dielectric layer, the metal lines having a top surface below a top surface of the dielectric layer; a hardmask layer on an upper portion of sidewalls of the metal lines, the hardmask layer having a portion extending between the metal lines, the extending portion being below the top surface of the metal lines; and at least one fully aligned via on the top surface of a given metal line.

公开(公告)号：US10727136B2

公开(公告)日：2020-07-28

申请号：US16185675

申请日：2018-11-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Ruilong Xie ,  Chanro Park ,  Laertis Economikos

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L21/768 ,  H01L29/417

Abstract: Methods of forming cross-coupling contacts for field-effect transistors and structures for field effect-transistors that include cross-coupling contacts. A dielectric cap is formed over a gate structure and a sidewall spacer adjacent to a sidewall of the gate structure. A portion of the dielectric cap is removed from over the sidewall spacer and the gate structure to expose a first portion of the gate electrode of the gate structure at a top surface of the gate structure. The sidewall spacer is then recessed relative to the gate structure to expose a portion of the gate dielectric layer at the sidewall of the gate structure, which is removed to expose a second portion of the gate electrode of the gate structure. A cross-coupling contact is formed that connects the first and second portions of the gate electrode of the gate structure with an epitaxial semiconductor layer adjacent to the sidewall spacer.

公开(公告)号：US10699957B2

公开(公告)日：2020-06-30

申请号：US16201449

申请日：2018-11-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Ruilong Xie ,  Jiehui Shu ,  Chanro Park ,  Laertis Economikos

IPC: H01L21/82 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/033 ,  H01L29/423 ,  H01L27/088 ,  H01L21/311 ,  H01L21/768 ,  H01L21/3105

Abstract: Methods of forming a structure that includes field-effect transistor and structures that include a field effect-transistor. A dielectric cap is formed over a gate structure of a field-effect transistor, and an opening is patterned that extends fully through the dielectric cap to divide the dielectric cap into a first section and a second section spaced across the opening from the first surface. First and second dielectric spacers are respectively selectively deposited on respective first and second surfaces of the first and second sections of the dielectric cap to shorten the opening. A portion of the gate structure exposed through the opening between the first and second dielectric spacers is etched to form a cut that divides the gate electrode into first and second sections disconnected by the cut. A dielectric material is deposited in the opening and in the cut to form a dielectric pillar.

公开(公告)号：US20200168509A1

公开(公告)日：2020-05-28

申请号：US16201449

申请日：2018-11-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Ruilong Xie ,  Jiehui Shu ,  Chanro Park ,  Laertis Economikos

IPC: H01L21/8234 ,  H01L21/311 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/033 ,  H01L29/423 ,  H01L27/088

Abstract: Methods of forming a structure that includes field-effect transistor and structures that include a field effect-transistor. A dielectric cap is formed over a gate structure of a field-effect transistor, and an opening is patterned that extends fully through the dielectric cap to divide the dielectric cap into a first section and a second section spaced across the opening from the first surface. First and second dielectric spacers are respectively selectively deposited on respective first and second surfaces of the first and second sections of the dielectric cap to shorten the opening. A portion of the gate structure exposed through the opening between the first and second dielectric spacers is etched to form a cut that divides the gate electrode into first and second sections disconnected by the cut. A dielectric material is deposited in the opening and in the cut to form a dielectric pillar.

公开(公告)号：US10658506B2

公开(公告)日：2020-05-19

申请号：US16038265

申请日：2018-07-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro Park ,  Kangguo Cheng

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/768 ,  H01L21/762 ,  H01L21/8234

Abstract: A fin cut last methodology for manufacturing a vertical FinFET includes forming a plurality of semiconductor fins over a substrate, forming shallow trench isolation between active fins and, following the formation of a functional gate of the active fins, using a selective etch to remove a sacrificial fin from within an isolation region. A further etching step can be used to remove a portion of the gate stack proximate to the sacrificial fin to create an isolation trench and a laterally-extending cavity within the isolation region that are back-filled with an isolation dielectric.

公开(公告)号：US20200152518A1

公开(公告)日：2020-05-14

申请号：US16185675

申请日：2018-11-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Ruilong Xie ,  Chanro Park ,  Laertis Economikos

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L21/768 ,  H01L29/40

Abstract: Methods of forming cross-coupling contacts for field-effect transistors and structures for field effect-transistors that include cross-coupling contacts. A dielectric cap is formed over a gate structure and a sidewall spacer adjacent to a sidewall of the gate structure. A portion of the dielectric cap is removed from over the sidewall spacer and the gate structure to expose a first portion of the gate electrode of the gate structure at a top surface of the gate structure. The sidewall spacer is then recessed relative to the gate structure to expose a portion of the gate dielectric layer at the sidewall of the gate structure, which is removed to expose a second portion of the gate electrode of the gate structure. A cross-coupling contact is formed that connects the first and second portions of the gate electrode of the gate structure with an epitaxial semiconductor layer adjacent to the sidewall spacer.

公开(公告)号：US10566248B1

公开(公告)日：2020-02-18

申请号：US16047044

申请日：2018-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel Chanemougame ,  Ruilong Xie ,  Chanro Park ,  Guillaume Bouche

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/06

Abstract: A method includes forming an isolation pillar between first and second active nanostructures for adjacent FETs. When a first WFM surrounding the second active nanostructure is removed as part of a WFM patterning process, creating a discontinuity in the first metal. The pillar or the discontinuity in the first metal on the part of the pillar prevent the etching from reaching and removing the first WFM on the first active nanostructure. The isolation pillar creates a gate cut isolation in a selected gate region, and can be shortened in another gate region to allow for gate sharing between adjacent FETs.

公开(公告)号：US10461196B2

公开(公告)日：2019-10-29

申请号：US15662526

申请日：2017-07-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Steven Bentley ,  Ruilong Xie ,  Min Gyu Sung

IPC: H01L29/786 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Forming a vertical FinFET includes forming a semiconductor fin on a substrate and having a fin mask on an upper surface thereof; laterally recessing the semiconductor fin causing the fin mask; forming a conformal gate liner on the recessed semiconductor fin and the fin mask, wherein the conformal gate liner includes a first portion surrounding the fin mask and a second portion surrounding the recessed fins and being separated from the fin mask by a thickness of the conformal gate liner; forming a gate mask laterally adjacent to the second portion of the conformal gate liner; removing the first portion of the conformal gate liner; removing the gate mask to expose a remaining second portion of the conformal gate liner; and forming a gate contact to the second portion of the conformal gate liner, the remaining second portion of the conformal gate liner defines the gate length.

公开(公告)号：US20190295898A1

公开(公告)日：2019-09-26

申请号：US16403745

申请日：2019-05-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Daniel Jaeger ,  Chanro Park ,  Laertis Economikos ,  Haiting Wang ,  Hui Zang

IPC: H01L21/8234 ,  H01L21/762 ,  H01L27/088 ,  H01L29/66 ,  H01L21/311

Abstract: Structures and methods of fabricating structures that include contacts coupled with a source/drain region of a field-effect transistor. Source/drain regions are formed adjacent to a temporary gate structure. A sacrificial layer may be disposed over the source/drain regions and a dielectric pillar is formed in the sacrificial layer between the source/drain regions, followed by deposition of a fill material, replacement of the temporary gate structure with a functional gate structure, and removal of the fill material. Alternatively, the fill material is formed first and the temporary gate structure is replaced by a functional gate structure; following removal of the fill material, a sacrificial layer is disposed over the source/drain regions and a dielectric pillar is formed in the sacrificial layer between the source/drain regions. A conductive layer having separate portions contacting the separate source/drain regions is formed, with the dielectric pillar separating the portions of the conductive layer.

公开(公告)号：US10388770B1

公开(公告)日：2019-08-20

申请号：US15924447

申请日：2018-03-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Christopher M. Prindle

IPC: H01L29/41 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L29/417

Abstract: One illustrative IC product disclosed herein includes a transistor device including a gate structure positioned above an active region, first and second conductive source/drain structures positioned adjacent opposite sidewalls of the gate structure and an insulating material positioned laterally between the gate structure and each of the first and second conductive source/drain structures. The product also includes first and second air gaps positioned adjacent opposite sidewalls of the gate structure, a gate contact structure that is positioned entirely above the active region and conductively coupled to the gate structure and a source/drain contact structure that is positioned entirely above the active region and conductively coupled to at least one of the first and second conductive source/drain structures.