公开(公告)号：US20090014727A1

公开(公告)日：2009-01-15

申请号：US12172701

申请日：2008-07-14

申请人： Sung-Man Kim ,  Young-Goo Song ,  Hyang-Shik Kong ,  Dong-Hyun Ki ,  Seong-Young Lee ,  Joo-Ae Yoon ,  Jong-Woong Chang

发明人： Sung-Man Kim ,  Young-Goo Song ,  Hyang-Shik Kong ,  Dong-Hyun Ki ,  Seong-Young Lee ,  Joo-Ae Yoon ,  Jong-Woong Chang

IPC分类号： H01L29/04 ,  H01L21/336

CPC分类号： H01L27/016 ,  G02F1/13458 ,  G02F1/136227 ,  H01L27/12 ,  H01L27/1244 ,  H01L27/1248 ,  H01L27/1288 ,  H01L27/3244 ,  H01L29/456 ,  H01L29/4908

摘要： A thin film array panel is provided, which includes: a plurality of signal lines including contact parts for contact with an external device; a plurality of thin film transistors connected to the signal lines; an insulating layer formed on the signal lines and the thin film transistors; and a plurality of pixel electrodes formed on the insulating layer and connected to the thin film transistors, wherein the insulating layer includes a contact portion disposed on the contact parts of the signal lines and having a thickness smaller than other portions and the contact portion of the insulating layer includes an inclined portion having an inclination angle smaller than about 45 degrees.

摘要翻译： 提供一种薄膜阵列面板，其包括：多条信号线，包括用于与外部装置接触的接触部分; 连接到信号线的多个薄膜晶体管; 形成在信号线和薄膜晶体管上的绝缘层; 以及形成在所述绝缘层上并连接到所述薄膜晶体管的多个像素电极，其中所述绝缘层包括设置在所述信号线的接触部分上并具有小于其它部分的厚度的接触部分，并且所述接触部分 绝缘层包括具有小于约45度的倾斜角度的倾斜部分。

公开(公告)号：US07288442B2

公开(公告)日：2007-10-30

申请号：US10634867

申请日：2003-08-06

申请人： Hyang-Shik Kong ,  Myung-Koo Hur ,  Chi-Woo Kim

发明人： Hyang-Shik Kong ,  Myung-Koo Hur ,  Chi-Woo Kim

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： G02F1/13439 ,  G02F1/13458 ,  H01L21/76801 ,  H01L21/76838 ,  H01L23/53209 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/458 ,  H01L2924/0002 ,  H01L2924/00

摘要： First, a conductive material of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed by depositing nitride silicon in the range of more than 300° C. for 5 minutes, and a semiconductor layer and an ohmic contact layer are sequentially formed. Next, a conductor layer of a metal such as Cr is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and patterned to form contact holes exposing the drain electrode, the gate pad and the data pad. Next, indium zinc oxide is deposited and patterned to form a pixel electrode, a redundant gate pad and a redundant data pad respectively connected to the drain electrode, the gate pad and the data pad.

摘要翻译： 首先，将铝基材料的导电材料沉积并图案化以形成包括栅极线，栅极焊盘和栅电极的栅极线。 通过在大于300℃的范围内沉积氮化硅5分钟形成栅极绝缘层，并依次形成半导体层和欧姆接触层。 接下来，沉积并图案化诸如Cr的金属的导体层以形成数据线，其包括与栅极线相交的数据线，源电极，漏电极和数据焊盘。 然后，沉积并图案化钝化层以形成暴露漏电极，栅极焊盘和数据焊盘的接触孔。 接下来，沉积并图案化氧化铟锌以形成分别连接到漏电极，栅极焊盘和数据焊盘的像素电极，冗余栅极焊盘和冗余数据焊盘。

公开(公告)号：US07221423B2

公开(公告)日：2007-05-22

申请号：US10991610

申请日：2004-11-17

申请人： Myung-Jae Park ,  Young-Joon Rhee ,  Hyeong-Jun Park ,  Hyang-Shik Kong

发明人： Myung-Jae Park ,  Young-Joon Rhee ,  Hyeong-Jun Park ,  Hyang-Shik Kong

IPC分类号： G02F1/1343

CPC分类号： G02F1/136286 ,  G02F1/133707 ,  G02F2001/13625

摘要： A thin film panel is provided, which includes: a substrate; a first signal line formed on the substrate; a second signal line that intersects the first signal line and includes first and second portions being substantially rectilinear and disposed on different straight lines and a connection connected to the first and the second portions; and first and second pixel electrodes disposed adjacent to the second signal line and overlapping the first and the second portions of the second signal line, respectively.

摘要翻译： 提供薄膜面板，其包括：基板; 形成在所述基板上的第一信号线; 第二信号线与第一信号线相交并且包括基本上直线的第一和第二部分，并且设置在不同的直线上，以及连接到第一和第二部分的连接; 以及与第二信号线相邻设置并与第二信号线的第一和第二部分重叠的第一和第二像素电极。

公开(公告)号：US20060054889A1

公开(公告)日：2006-03-16

申请号：US10942039

申请日：2004-09-16

申请人： Jang-Soo Kim ,  Hyang-Shik Kong ,  Hye-Young Ryu ,  Sung-Man Kim

发明人： Jang-Soo Kim ,  Hyang-Shik Kong ,  Hye-Young Ryu ,  Sung-Man Kim

IPC分类号： H01L29/04

CPC分类号： H01L27/124 ,  G02F1/136213 ,  G02F1/136259 ,  G02F2001/13629 ,  H01L27/1255 ,  H01L27/1288

摘要： A thin film transistor array panel comprising: an insulating substrate; a plurality of gate lines formed on the insulating substrate and including a plurality of gate electrodes and end portions; a plurality of storage electrode lines formed on the insulating substrate; a gate insulating layer formed on the gate lines and storage electrode lines; a semiconductor layer formed on the gate insulating layer; a ohmic contact layer formed on the semiconductor layer; a plurality of data lines formed on the gate insulating layer, intersecting the gate lines to define a display area, and having source electrodes and end portions; a plurality of drain electrodes facing the source electrodes; a passivation layer formed on the data lines and drain electrodes and having contact holes; a plurality of pixel electrodes formed on the passivation layer and connected to the drain electrodes through the contact holes; a storage line connecting bar connecting the storage electrode lines; and a redundant connecting line connecting the storage electrode lines is provided.

摘要翻译： 1.一种薄膜晶体管阵列面板，包括：绝缘基板; 多个栅极线，形成在所述绝缘基板上并且包括多个栅电极和端部; 形成在所述绝缘基板上的多个存储电极线; 形成在栅极线和存储电极线上的栅极绝缘层; 形成在所述栅极绝缘层上的半导体层; 形成在所述半导体层上的欧姆接触层; 形成在所述栅极绝缘层上的多条数据线，与所述栅极线交叉以限定显示区域，并具有源电极和端部; 面对所述源电极的多个漏电极; 形成在数据线和漏电极上并具有接触孔的钝化层; 多个像素电极，形成在钝化层上并通过接触孔连接到漏电极; 连接存储电极线的存储线连接条; 并且提供连接存储电极线的冗余连接线。

公开(公告)号：US06518630B2

公开(公告)日：2003-02-11

申请号：US09988169

申请日：2001-11-19

申请人： Chun-Gi You ,  Hyang-Shik Kong

发明人： Chun-Gi You ,  Hyang-Shik Kong

IPC分类号： H01L310392

CPC分类号： H01L27/12 ,  G02F1/136227 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/458

摘要： A thin film transistor array substrate includes a substrate, a gate wire with a gate line and a gate electrode formed on the substrate, a gate insulating layer covering the gate wire, and a semiconductor pattern formed on the gate insulating layer. A data wire is formed on the gate insulating layer and the semiconductor pattern with a data line, and a source electrode and a drain electrode. The data wire bears a multiple-layered structure having a metallic layer and an intermetallic compound layer. A protective layer is formed on the data wire and the semiconductor pattern. A pixel electrode is formed on the protective layer while contacting the drain electrode through a contact hole.

公开(公告)号：US08796680B2

公开(公告)日：2014-08-05

申请号：US13464125

申请日：2012-05-04

申请人： Sang-Ki Kwak ,  Hyang-Shik Kong ,  Sun-Il Kim

发明人： Sang-Ki Kwak ,  Hyang-Shik Kong ,  Sun-Il Kim

IPC分类号： H01L29/26

CPC分类号： H01L27/1288 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/7869

摘要： A thin-film transistor (TFT) substrate includes a semiconductor pattern, a conductive pattern, a first wiring pattern, an insulation pattern and a second wiring pattern. The semiconductor pattern is formed on a substrate. The conductive pattern is formed as a layer identical to the semiconductor pattern on the substrate. The first wiring pattern is formed on the semiconductor pattern. The first wiring pattern includes a source electrode and a drain electrode spaced apart from the source electrode. The insulation pattern is formed on the substrate having the first wiring pattern to cover the first wiring pattern. The second wiring pattern is formed on the insulation pattern. The second wiring pattern includes a gate electrode formed on the source and drain electrodes. Therefore, a TFT substrate is manufactured using two or three masks, so that manufacturing costs may be decreased.

摘要翻译： 薄膜晶体管（TFT）衬底包括半导体图案，导电图案，第一布线图案，绝缘图案和第二布线图案。 半导体图案形成在基板上。 导电图案形成为与衬底上的半导体图案相同的层。 第一布线图案形成在半导体图案上。 第一布线图案包括与源电极间隔开的源电极和漏电极。 在具有第一布线图案的基板上形成绝缘图案以覆盖第一布线图案。 第二布线图案形成在绝缘图案上。 第二布线图案包括形成在源极和漏极上的栅电极。 因此，使用两个或三个掩模制造TFT基板，从而可以降低制造成本。

公开(公告)号：US08427623B2

公开(公告)日：2013-04-23

申请号：US12816591

申请日：2010-06-16

申请人： Se-Hwan Yu ,  Hyang-Shik Kong ,  Su-Hyoung Kang

发明人： Se-Hwan Yu ,  Hyang-Shik Kong ,  Su-Hyoung Kang

IPC分类号： G02F1/1333 ,  G02F1/1343 ,  G02F1/1345

CPC分类号： G02F1/136286 ,  G02F2001/13629

摘要： A thin film transistor array panel including a display area having a gate line, a data line insulated from and intersecting the gate line, a thin film transistor connected to the gate line and the data line, and a pixel electrode connected to the thin film transistor, and a peripheral area formed on the circumference of the display area, according to an exemplary embodiment of the present invention, includes: a driving signal line formed with the same layer as the gate line in the peripheral area and receiving an external signal; a connection signal line formed with the same layer as the data line in the peripheral area; a disconnection prevention member overlapping the side surface of the connection signal line on the connection signal line; and a connection assistance member formed on the disconnection prevention member and connecting the driving signal line and the connection signal line.

摘要翻译： 一种薄膜晶体管阵列面板，包括具有栅极线的显示区域，与栅极线绝缘并与之相交的数据线，连接到栅极线和数据线的薄膜晶体管，以及连接到薄膜晶体管的像素电极 以及形成在显示区域的圆周上的周边区域，根据本发明的示例性实施例，包括：形成与周边区域中的栅极线相同层并且接收外部信号的驱动信号线; 连接信号线，其与周边区域中的数据线形成相同的层; 断开防止部件与连接信号线上的连接信号线的侧面重叠; 以及连接辅助构件，其形成在所述防止断开构件上并且连接所述驱动信号线和所述连接信号线。

公开(公告)号：US08355088B2

公开(公告)日：2013-01-15

申请号：US13372016

申请日：2012-02-13

申请人： Dong-Gyu Kim ,  Hyang-Shik Kong ,  Jang-Soo Kim

发明人： Dong-Gyu Kim ,  Hyang-Shik Kong ,  Jang-Soo Kim

IPC分类号： G02F1/136 ,  G02F1/1343

CPC分类号： G02F1/136213 ,  G02F1/1337 ,  G02F1/133784 ,  G02F1/134336 ,  G02F1/136227 ,  G02F2201/123

摘要： A TFT array panel includes an insulating substrate, a gate line, a storage electrode line, a gate insulating layer, a semiconductor island formed on the gate insulating layer, and a data line and a drain electrode formed thereon. The data line and drain electrode are covered with a passivation layer. A pixel electrode is formed on the passivation layer and connected to the drain electrode through a contact hole. The TFT array panel is covered with an alignment layer rubbed approximately in a direction from the upper left corner to lower right corner of the TFT array panel or the pixel electrodes. The pixel electrode overlaps the gate line and data line and has an expansion located near the upper left corner of the pixel electrode to increase the width of the corresponding overlapping area between the pixel electrode and the gate line and/or data line.

摘要翻译： TFT阵列面板包括绝缘基板，栅极线，存储电极线，栅极绝缘层，形成在栅极绝缘层上的半导体岛，以及形成在其上的数据线和漏电极。 数据线和漏电极被钝化层覆盖。 像素电极形成在钝化层上并通过接触孔连接到漏电极。 TFT阵列面板被覆盖有大致沿着TFT阵列板的左上角或右下角或像素电极的方向摩擦的取向层。 像素电极与栅极线和数据线重叠，并且具有位于像素电极的左上角附近的扩展，以增加像素电极与栅极线和/或数据线之间的相应重叠区域的宽度。

公开(公告)号：US20120178197A1

公开(公告)日：2012-07-12

申请号：US13372016

申请日：2012-02-13

申请人： DONG-GYU KIM ,  Hyang-Shik Kong ,  Jang-Soo Kim

发明人： DONG-GYU KIM ,  Hyang-Shik Kong ,  Jang-Soo Kim

IPC分类号： H01L33/08

CPC分类号： G02F1/136213 ,  G02F1/1337 ,  G02F1/133784 ,  G02F1/134336 ,  G02F1/136227 ,  G02F2201/123

摘要： A TFT array panel includes an insulating substrate, a gate line, a storage electrode line, a gate insulating layer, a semiconductor island formed on the gate insulating layer, and a data line and a drain electrode formed thereon. The data line and drain electrode are covered with a passivation layer. A pixel electrode is formed on the passivation layer and connected to the drain electrode through a contact hole. The TFT array panel is covered with an alignment layer rubbed approximately in a direction from the upper left corner to lower right corner of the TFT array panel or the pixel electrodes. The pixel electrode overlaps the gate line and data line and has an expansion located near the upper left corner of the pixel electrode to increase the width of the corresponding overlapping area between the pixel electrode and the gate line and/or data line.

摘要翻译： TFT阵列面板包括绝缘基板，栅极线，存储电极线，栅极绝缘层，形成在栅极绝缘层上的半导体岛，以及形成在其上的数据线和漏电极。 数据线和漏电极被钝化层覆盖。 像素电极形成在钝化层上并通过接触孔连接到漏电极。 TFT阵列面板被覆盖有大致沿着TFT阵列板的左上角或右下角或像素电极的方向摩擦的取向层。 像素电极与栅极线和数据线重叠，并且具有位于像素电极的左上角附近的扩展，以增加像素电极与栅极线和/或数据线之间的相应重叠区域的宽度。

公开(公告)号：US20120139866A1

公开(公告)日：2012-06-07

申请号：US13155227

申请日：2011-06-07

申请人： Suk-Won JUNG ,  Hyang-Shik Kong ,  Sung-Hoon Yang ,  Sang-Youn Han ,  Kyung-Sook Jeon ,  Seung-Mi Seo ,  Mi-Seon Seo

发明人： Suk-Won JUNG ,  Hyang-Shik Kong ,  Sung-Hoon Yang ,  Sang-Youn Han ,  Kyung-Sook Jeon ,  Seung-Mi Seo ,  Mi-Seon Seo

IPC分类号： G06F3/044 ,  H01L31/18

CPC分类号： H01L31/112 ,  G02F1/133345 ,  G02F1/13338 ,  G02F1/133512 ,  G02F1/1368 ,  G06F3/0421 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1443 ,  H01L27/1446 ,  H01L27/14678 ,  H01L29/66765 ,  H01L31/167

摘要： A display substrate includes a pixel switching element, a pixel electrode, a reference line, a control switching element, a bias line, a light sensing element, a sensing capacitor and a light blocking filter pattern. The pixel switching element is connected to a data line and a gate line, includes a first semiconductor pattern. The pixel electrode is connected to the pixel switching element. The reference line is in parallel with the data line. The control switching element is connected to the reference line and the gate line, includes a second semiconductor pattern. The bias line is in parallel with the gate line. The light sensing element is connected to the bias line and the control switching element, includes a third semiconductor pattern. The sensing capacitor is connected to the light sensing element and a storage line. The light blocking filter pattern transmits a first light, and blocks a second light.

摘要翻译： 显示基板包括像素开关元件，像素电极，参考线，控制开关元件，偏置线，感光元件，感测电容器和遮光滤光片图案。 像素开关元件连接到数据线和栅极线，包括第一半导体图案。 像素电极连接到像素开关元件。 参考线与数据线并行。 控制开关元件连接到参考线并且栅极线包括第二半导体图案。 偏置线与栅极线并联。 光感测元件连接到偏置线并且控制开关元件包括第三半导体图案。 感测电容器连接到光感测元件和存储线。 遮光滤光片图案透射第一光，并阻挡第二光。