公开(公告)号：US20200343379A1

公开(公告)日：2020-10-29

申请号：US16634517

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Abhishek A. SHARMA ,  Van H. LE ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Gilbert DEWEY ,  Shriram SHIVARAMAN ,  Inanc MERIC ,  Benjamin CHU-KUNG

IPC: H01L29/786 ,  H01L29/51 ,  H01L27/108 ,  H01L27/24 ,  H01L29/66

Abstract: Embodiments herein describe techniques for a semiconductor device, which may include a substrate, a metallic encapsulation layer above the substrate, and a gate electrode above the substrate and next to the metallic encapsulation layer. A channel layer may be above the metallic encapsulation layer and the gate electrode, where the channel layer may include a source area and a drain area. In addition, a source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area. Other embodiments may be described and/or claimed.

公开(公告)号：US20200312973A1

公开(公告)日：2020-10-01

申请号：US16651955

申请日：2017-12-21

Applicant: Intel Corporation

Inventor： Sean T. MA ,  Abhishek SHARMA ,  Gilbert DEWEY ,  Van H. LE ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Benjamin CHU-KUNG ,  Shriram SHIVARAMAN

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/786

Abstract: This disclosure illustrates a transistor with dual gate workfunctions. The transistor with dual gate workfunctions may comprise a source region, a drain region, a channel between the source region and the drain region, and a gate to control a conductivity of the channel. The gate may comprise a first portion with a first workfunction and a second portion with a second workfunction. One of the portions is nearer the source region than the other portion. The workfunction of the portion nearer the source provides a lower thermionic barrier than the workfunction of the portion further away from the source.

公开(公告)号：US20200227568A1

公开(公告)日：2020-07-16

申请号：US16638301

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Van H. LE ,  Abhishek A. SHARMA ,  Benjamin CHU-KUNG ,  Gilbert DEWEY ,  Ravi PILLARISETTY ,  Miriam R. RESHOTKO ,  Shriram SHIVARAMAN ,  Li Huey TAN ,  Tristan A. TRONIC ,  Jack T. KAVALIEROS

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/417 ,  H01L29/40

Abstract: Embodiments herein describe techniques for a semiconductor device, which may include a substrate, and a U-shaped channel above the substrate. The U-shaped channel may include a channel bottom, a first channel wall and a second channel wall parallel to each other, a source area, and a drain area. A gate dielectric layer may be above the substrate and in contact with the channel bottom. A gate electrode may be above the substrate and in contact with the gate dielectric layer. A source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area. Other embodiments may be described and/or claimed.

公开(公告)号：US20200066912A1

公开(公告)日：2020-02-27

申请号：US16325164

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Van H. LE ,  Rafael RIOS ,  Shriram SHIVARAMAN ,  Jack T. KAVALIEROS ,  Marko RADOSAVLJEVIC

IPC: H01L29/786 ,  H01L29/221 ,  H01L29/66

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing bi-layer semiconducting oxides in a source/drain for low access and contact resistance of thin film transistors. For instance, there is disclosed in accordance with one embodiment a semiconductor device having therein a substrate; a bi-layer oxides layer formed from a first oxide material and a second oxide material, the first oxide material comprising a semiconducting oxide material and having different material properties from the second oxide material comprising a high mobility oxide material; a channel layer formed atop the substrate, the channel layer formed from the semiconducting oxide material of the bi-layer oxides layer; a high mobility oxide layer formed atop the channel layer, the high conductivity oxide layer formed from the high mobility oxide material of the bi-layer oxides layer; metallic contacts formed atop the high mobility oxide layer; a gate and a gate oxide material formed atop the high mobility oxide layer, the gate oxide material being in direct contact with the high mobility oxide layer; and spacers separating the metallic contacts from the gate and gate oxide material. Other related embodiments are disclosed.

公开(公告)号：US20200006570A1

公开(公告)日：2020-01-02

申请号：US16024687

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Van H. LE ,  Rajat PAUL ,  Abhishek SHARMA ,  Tahir GHANI ,  Jack KAVALIEROS ,  Gilbert DEWEY ,  Matthew METZ ,  Miriam RESHOTKO ,  Benjamin CHU-KUNG ,  Justin WEBER ,  Shriram SHIVARAMAN

IPC: H01L29/786 ,  H01L29/45

Abstract: Embodiments of the present disclosure are contact structures for thin film transistor (TFT) devices. One embodiment is a TFT device comprising: a substrate; a gate formed above the substrate; a TFT channel formed above the substrate; and a pair of contacts formed on the TFT channel, wherein each of the contacts comprises one or more layers including: a metal that is non-reactive with a material of the TFT channel; or a plurality of layers including a first metal layer formed on a second layer, the second layer in contact with the TFT channel and between the first mater layer and the TFT channel. Other embodiments may be disclosed and/or claimed.

公开(公告)号：US20200006523A1

公开(公告)日：2020-01-02

申请号：US16024699

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Matthew METZ ,  Willy RACHMADY ,  Sean MA ,  Jessica TORRES ,  Nicholas MINUTILLO ,  Cheng-Ying HUANG ,  Anand MURTHY ,  Harold KENNEL ,  Gilbert DEWEY ,  Jack KAVALIEROS ,  Tahir GHANI

IPC: H01L29/66 ,  H01L21/02

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device including a substrate with a surface that is substantially flat. A channel area including an III-V compound may be above the substrate, where the channel area is an epitaxial layer directly in contact with the surface of the substrate. A gate dielectric layer is adjacent to the channel area and in direct contact with the channel area, while a gate electrode is adjacent to the gate dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20190393356A1

公开(公告)日：2019-12-26

申请号：US16016381

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Van H. LE ,  Seung Hoon SUNG ,  Benjamin CHU-KUNG ,  Miriam RESHOTKO ,  Matthew METZ ,  Yih WANG ,  Gilbert DEWEY ,  Jack KAVALIEROS ,  Tahir GHANI ,  Nazila HARATIPOUR ,  Abhishek SHARMA ,  Shriram SHIVARAMAN

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L27/108 ,  H01L23/522 ,  H01L29/66

Abstract: Embodiments herein describe techniques for a semiconductor device including a transistor. The transistor includes a first metal contact as a source electrode, a second metal contact as a drain electrode, a channel area between the source electrode and the drain electrode, and a third metal contact aligned with the channel area as a gate electrode. The first metal contact may be located in a first metal layer along a first direction. The second metal contact may be located in a second metal layer along the first direction, in parallel with the first metal contact. The third metal contact may be located in a third metal layer along a second direction substantially orthogonal to the first direction. The third metal layer is between the first metal layer and the second metal layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20190393267A1

公开(公告)日：2019-12-26

申请号：US16480598

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Ravi PILLARISETTY ,  Abhishek A. SHARMA ,  Van H. LE ,  Gilbert DEWEY ,  Jack T. KAVALIEROS

IPC: H01L27/24 ,  H01L27/108 ,  H01L27/22 ,  H01L29/78 ,  H01L29/66 ,  H01L43/12 ,  H01L45/00

Abstract: A programmable array including a plurality of cells aligned in a row on a substrate, wherein each of the plurality of cells includes a programmable element and a transistor, the transistor including a body including a first diffusion region and a second diffusion region on the first diffusion region and separated by a channel and the programmable element is disposed on the second diffusion region and includes a width dimension equivalent to a width dimension of the body of the transistor. A method of forming an integrated circuit including forming bodies in a plurality rows on a substrate, each of the bodies including a programmable element and a first diffusion region, a second diffusion region and a channel of a transistor; forming a masking material as a plurality of rows across the bodies; etching the bodies through the masking material; and replacing the masking material with an address line material.

公开(公告)号：US20190393214A1

公开(公告)日：2019-12-26

申请号：US16017971

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Aaron LILAK ,  Patrick MORROW ,  Gilbert DEWEY ,  Willy RACHMADY ,  Rishabh MEHANDRU

IPC: H01L27/06 ,  H01L29/78 ,  H01L29/06 ,  H01L23/522 ,  H01L21/8234 ,  H01L21/822 ,  H01L27/02

Abstract: Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a lower device layer that includes a first transistor structure, an upper device layer above the lower device layer including a second transistor structure, and an isolation wall that extends between the upper device layer and the lower device layer. The isolation wall may be in contact with an edge of a first gate structure of the first transistor structure and an edge of a second gate structure of the second transistor structure, and may have a first width to the edge of the first gate structure at the lower device layer, and a second width to the edge of the second gate structure at the upper device layer. The first width may be different from the second width. Other embodiments may be described and/or claimed.

公开(公告)号：US20190296145A1

公开(公告)日：2019-09-26

申请号：US16316337

申请日：2016-09-26

Applicant: Intel Corporation

Inventor： Cheng-Ying HUANG ,  Willy RACHMADY ,  Matthew V. METZ ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Sean T. MA ,  Harold KENNEL

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L29/417 ,  H01L29/20

Abstract: A buffer layer is deposited on a substrate. A first III-V semiconductor layer is deposited on the buffer layer. A second III-V semiconductor layer is deposited on the first III-V semiconductor layer. The second III-V semiconductor layer comprises a channel portion and a source/drain portion. The first III-V semiconductor layer acts as an etch stop layer to etch a portion of the second III-V semiconductor layer to form the source/drain portion.