公开(公告)号：US09032141B2

公开(公告)日：2015-05-12

申请号：US13690523

申请日：2012-11-30

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  John B. Halbert

IPC: G06F12/00 ,  G11C11/406 ,  G11C11/4078 ,  G11C11/408 ,  G11C29/50 ,  G06F13/16

CPC classification number: G11C11/40611 ,  G06F13/1636 ,  G11C7/24 ,  G11C11/4078 ,  G11C11/408 ,  G11C29/50 ,  G11C29/50012

Abstract: Detection logic of a memory subsystem obtains a threshold for a memory device that indicates a number of accesses within a time window that causes risk of data corruption on a physically adjacent row. The detection logic obtains the threshold from a register that stores configuration information for the memory device, and can be a register on the memory device itself and/or can be an entry of a configuration storage device of a memory module to which the memory device belongs. The detection logic determines whether a number of accesses to a row of the memory device exceeds the threshold. In response to detecting the number of accesses exceeds the threshold, the detection logic can generate a trigger to cause the memory device to perform a refresh targeted to a physically adjacent victim row.

Abstract translation: 存储器子系统的检测逻辑获得存储器设备的阈值，该存储器设备指示在时间窗口内的数量的访问，导致物理上相邻的行上的数据损坏风险。 检测逻辑从存储器件的配置信息的寄存器获得阈值，并且可以是存储器件本身的寄存器和/或可以是存储器件所属的存储器模块的配置存储设备的条目 。 检测逻辑确定对存储器件的行的访问次数是否超过阈值。 响应于检测到的访问次数超过阈值，检测逻辑可以产生触发以使存储器件执行针对物理上相邻的受害者行的刷新。

公开(公告)号：US20150089111A1

公开(公告)日：2015-03-26

申请号：US14560976

申请日：2014-12-04

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  Klaus J. Ruff ,  George Vergis ,  Suneeta Sah

IPC: G06F13/28 ,  G06F13/16

CPC classification number: G11C7/1072 ,  G06F11/073 ,  G06F11/0787 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1016 ,  G06F11/1612 ,  G06F13/16 ,  G06F13/28 ,  G11C7/1006 ,  G11C29/44 ,  G11C2029/0411 ,  G11C2029/4402

Abstract: A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device.

Abstract translation: 通过将地址总线上的数据传送到连接到数据总线的设备，可以读取未连接到数据总线的寄存器，数据由连接到数据总线的设备读取。 寄存器位于通过地址总线连接到连接到地址总线和数据总线两者的存储器件的寄存器中。 主处理器触发寄存器设备通过地址总线将信息传送到存储器设备上的寄存器。 然后主机处理器从存储器件的寄存器读取信息。

公开(公告)号：US12164373B2

公开(公告)日：2024-12-10

申请号：US17339754

申请日：2021-06-04

Applicant: Intel Corporation

Inventor： Bill Nale ,  Kuljit S. Bains ,  Lawrence Blankenbeckler ,  Ronald Anderson ,  Jongwon Lee

IPC: G06F11/00 ,  G06F11/10 ,  G11C11/406 ,  G11C11/4096

Abstract: A memory chip is described. The memory chip includes storage cells along a row of the memory chip's storage cell array to store a count value of the row's activations and error correction code (ECC) information to protect the count value. The memory chip includes ECC read logic circuitry to correct an error in the count value. The memory chip includes a comparator to compare the count value against a threshold. The memory chip includes circuitry to increment the count value if the count value is deemed not to have reached the threshold and ECC write logic circuitry to determine new ECC information for the incremented count value, and write driver circuitry to write the incremented count value and the new ECC information into the storage cells. The memory chip includes circuitry to cause the row to be refreshed if the count value is deemed to have reached the threshold.

公开(公告)号：US11704194B2

公开(公告)日：2023-07-18

申请号：US17530086

申请日：2021-11-18

Applicant: Intel Corporation

Inventor： Kuljit S. Bains

IPC: G06F11/00 ,  G06F11/10 ,  G06F13/16

CPC classification number: G06F11/1068 ,  G06F13/1668

Abstract: A memory device that performs internal ECC (error checking and correction) can treat an N-bit channel as two N/2-bit channels for application of ECC. The memory device includes a memory array to store data and prefetches data bits and error checking and correction (ECC) bits from the memory array for a memory access operation. The memory device includes internal ECC hardware to apply ECC, with a first group of a first half the data bits checked by a first half of the ECC bits in parallel with a second group of a second half of the data bits checked by a second half of the ECC bits.

公开(公告)号：US10789010B2

公开(公告)日：2020-09-29

申请号：US15282757

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： George Vergis ,  Kuljit S. Bains

IPC: G06F3/06 ,  G11C7/10 ,  G06F13/16 ,  G11C11/4076 ,  G11C11/4093

Abstract: A memory subsystem includes a command address bus capable to be operated at double data rate. A memory circuit includes N command signal lines that operate at a data rate of 2R to receive command information from a memory controller. The memory circuit includes 2N command signal lines that operate at a data rate of R to transfer the commands to one or more memory devices. While ratios of 1:2 are specified, similar techniques can be used to send command signals at higher data rates over fewer signal lines from a host to a logic circuit, which then transfers the command signals at lower data rates over more signal lines.

公开(公告)号：US10242727B2

公开(公告)日：2019-03-26

申请号：US15983009

申请日：2018-05-17

Applicant: Intel Corporation

Inventor： Christopher E. Cox ,  Kuljit S. Bains ,  John B. Halbert

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/409 ,  G11C7/08 ,  G11C16/34 ,  G11C16/26 ,  G11C16/10 ,  G11C16/04 ,  G11C16/24

Abstract: Devices, systems, and methods include an active mode to accommodate read/write operations of a memory device and a self-refresh mode to accommodate recharging of voltage levels representing stored data when read/write operations are idle. At least one register source provides a first voltage level and a second voltage level that is less than the first voltage level. With such a configuration, during the active mode, the memory device operates at the first voltage level as provided by the at least one register source, and during the self-refresh mode, the memory device operates at the second voltage level as provided by the at least one register source.

公开(公告)号：US10210925B2

公开(公告)日：2019-02-19

申请号：US15835050

申请日：2017-12-07

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  John B. Halbert ,  Christopher P. Mozak ,  Theodore Z. Schoenborn ,  Zvika Greenfield

IPC: G06F12/00 ,  G11C11/4091 ,  G11C11/406 ,  G06F3/06

Abstract: A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

公开(公告)号：US10033382B2

公开(公告)日：2018-07-24

申请号：US15423431

申请日：2017-02-02

Applicant: Intel Corporation

Inventor： James A. McCall ,  Kuljit S. Bains

IPC: H03K19/00 ,  G11C11/4093 ,  G11C11/4074

Abstract: Described herein are a method and an apparatus for dynamically switching between one or more finite termination impedance value settings to a memory input-output (I/O) interface of a memory in response to a termination signal level. The method comprises: setting a first termination impedance value setting for a termination unit of an input-output (I/O) interface of a memory; assigning the first termination impedance value setting to the termination unit when the memory is not being accessed; and switching from the first termination impedance value setting to a second termination impedance value setting in response to a termination signal level.

公开(公告)号：US09934143B2

公开(公告)日：2018-04-03

申请号：US14038659

申请日：2013-09-26

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  Suneeta Sah ,  John H. Crawford ,  Brian S. Morris

IPC: G06F13/12 ,  G06F12/06 ,  G06F12/02

CPC classification number: G06F12/06 ,  G06F12/0292 ,  G06F12/0638

Abstract: A memory subsystem includes a group of memory devices connected to an address bus. The memory subsystem includes logic to uniquely map a physical address of a memory access command to each memory device of the group. Thus, each physical address sent by an associated memory controller uniquely accesses a different row of each memory device, instead of being mapped to the same or corresponding row of each memory device.

公开(公告)号：US09904591B2

公开(公告)日：2018-02-27

申请号：US14918428

申请日：2015-10-20

Applicant: Intel Corporation

Inventor： John B. Halbert ,  Kuljit S. Bains ,  Debaleena Das ,  Bill Nale

IPC: G11C29/00 ,  G06F11/10 ,  G06F11/07 ,  G06F13/00 ,  G06F11/08

CPC classification number: G06F11/1004 ,  G06F11/073 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/08 ,  G06F13/00

Abstract: Techniques and mechanisms to provide selective access to data error information by a memory controller. In an embodiment, a memory device stores a first value representing a baseline number of data errors determined prior to operation of the memory device with the memory controller. Error detection logic of the memory device determines a current count of data errors, and calculates a second value representing a difference between the count of data errors and the baseline number of data errors. The memory device provides the second value to the memory controller, which is unable to identify that the second value is a relative error count. In another embodiment, the memory controller is restricted from retrieving the baseline number of data errors.