公开(公告)号：US20190044886A1

公开(公告)日：2019-02-07

申请号：US15941943

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Anil Rao ,  Suraj Prabhakaran ,  Mohan Kumar ,  Karthik Kumar

IPC: H04L12/947 ,  H04L12/931 ,  H04L12/801 ,  H04L12/66

Abstract: Technologies for accelerating edge device workloads at a device edge network include a network computing device which includes a processor platform that includes at least one processor which supports a plurality of non-accelerated function-as-a-service (FaaS) operations and an accelerated platform that includes at least one accelerator which supports a plurality of accelerated FaaS (AFaaS) operation. The network computing device is configured to receive a request to perform a FaaS operation, determine whether the received request indicates that an AFaaS operation is to be performed on the received request, and identify compute requirements for the AFaaS operation to be performed. The network computing device is further configured to select an accelerator platform to perform the identified AFaaS operation and forward the received request to the selected accelerator platform to perform the identified AFaaS operation. Other embodiments are described and claimed.

公开(公告)号：US20190034340A1

公开(公告)日：2019-01-31

申请号：US15855104

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Kshitij A. Doshi ,  Francesc Guim Bernat ,  Daniel Rivas Barragan ,  Suraj Prabhakaran

IPC: G06F12/0831 ,  G06F17/30 ,  G06F13/16

Abstract: An embodiment of a semiconductor package apparatus may include technology to create a tracking structure for a memory controller to track a range of memory addresses of a persistent memory, identify a write request at the memory controller for a memory location within the range of tracked memory addresses, and set a flag in the tracking structure to indicate that the memory location had the identified write request. Other embodiments are disclosed and claimed.

公开(公告)号：US20250097306A1

公开(公告)日：2025-03-20

申请号：US18894452

申请日：2024-09-24

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Patrick Bohan ,  Kshitij Arun Doshi ,  Brinda Ganesh ,  Andrew J. Herdrich ,  Monica Kenguva ,  Karthik Kumar ,  Patrick G. Kutch ,  Felipe Pastor Beneyto ,  Rashmin Patel ,  Suraj Prabhakaran ,  Ned M. Smith ,  Petar Torre ,  Alexander Vul

IPC: H04L67/148 ,  G06F9/48 ,  H04L41/5003 ,  H04L41/5019 ,  H04L43/0811 ,  H04L47/70 ,  H04L67/00 ,  H04L67/10 ,  H04W4/40 ,  H04W4/70

Abstract: An architecture to perform resource management among multiple network nodes and associated resources is disclosed. Example resource management techniques include those relating to: proactive reservation of edge computing resources; deadline-driven resource allocation; speculative edge QOS pre-allocation; and automatic QoS migration across edge computing nodes. In a specific example, a technique for service migration includes: identifying a service operated with computing resources in an edge computing system, involving computing capabilities for a connected edge device with an identified service level; identifying a mobility condition for the service, based on a change in network connectivity with the connected edge device; and performing a migration of the service to another edge computing system based on the identified mobility condition, to enable the service to be continued at the second edge computing apparatus to provide computing capabilities for the connected edge device with the identified service level.

公开(公告)号：US12132805B2

公开(公告)日：2024-10-29

申请号：US17542175

申请日：2021-12-03

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Petar Torre ,  Ned Smith ,  Brinda Ganesh ,  Evan Custodio ,  Suraj Prabhakaran

IPC: H04L67/60 ,  H04L12/66 ,  H04L47/70 ,  H04L67/2885 ,  H04L67/5681 ,  H04L67/62

CPC classification number: H04L67/60 ,  H04L12/66 ,  H04L47/70 ,  H04L67/2885 ,  H04L67/5681 ,  H04L67/62

Abstract: Technologies for fulfilling service requests in an edge architecture include an edge gateway device to receive a request from an edge device or an intermediate tier device of an edge network to perform a function of a service by an entity hosting the service. The edge gateway device is to identify one or more input data to fulfill the request by the service and request the one or more input data from an edge resource identified to provide the input data. The edge gateway device is to provide the input data to the entity associated with the request.

公开(公告)号：US12038861B2

公开(公告)日：2024-07-16

申请号：US17973268

申请日：2022-10-25

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Da-Ming Chiang ,  Kshitij A. Doshi ,  Suraj Prabhakaran ,  Mark A. Schmisseur

IPC: G06F13/40 ,  G06F9/455 ,  G06F9/50 ,  G06F9/54 ,  G06F13/362 ,  G06F13/42 ,  G06N3/02 ,  G06N3/04 ,  G06N3/045 ,  G06N3/08

CPC classification number: G06F13/4068 ,  G06F9/45533 ,  G06F9/5027 ,  G06F9/54 ,  G06F13/362 ,  G06F13/4265 ,  G06F13/4282 ,  G06N3/02 ,  G06N3/04 ,  G06N3/045 ,  G06N3/08 ,  G06F2213/0026

Abstract: There is disclosed an example of an artificial intelligence (AI) system, including: a first hardware platform; a fabric interface configured to communicatively couple the first hardware platform to a second hardware platform; a processor hosted on the first hardware platform and programmed to operate on an AI problem; and a first training accelerator, including: an accelerator hardware; a platform inter-chip link (ICL) configured to communicatively couple the first training accelerator to a second training accelerator on the first hardware platform without aid of the processor; a fabric ICL to communicatively couple the first training accelerator to a third training accelerator on a second hardware platform without aid of the processor; and a system decoder configured to operate the fabric ICL and platform ICL to share data of the accelerator hardware between the first training accelerator and second and third training accelerators without aid of the processor.

公开(公告)号：US20230222363A1

公开(公告)日：2023-07-13

申请号：US18091874

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Suraj Prabhakaran ,  Kshitij Arun Doshi ,  Da-Ming Chiang ,  Joe Cahill

IPC: G06N5/04

CPC classification number: G06N5/04

Abstract: Various systems and methods of initiating and performing contextualized AI inferencing, are described herein. In an example, operations performed with a gateway computing device to invoke an inferencing model include receiving and processing a request for an inferencing operation, selecting an implementation of the inferencing model on a remote service based on a model specification and contextual data from the edge device, and executing the selected implementation of the inferencing model, such that results from the inferencing model are provided back to the edge device. Also in an example, operations performed with an edge computing device to request an inferencing model include collecting contextual data, generating an inferencing request, transmitting the inference request to a gateway device, and receiving and processing the results of execution. Further techniques for implementing a registration of the inference model, and invoking particular variants of an inference model, are also described.

公开(公告)号：US11586575B2

公开(公告)日：2023-02-21

申请号：US17584092

申请日：2022-01-25

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Da-Ming Chiang ,  Kshitij A. Doshi ,  Suraj Prabhakaran ,  Mark A. Schmisseur

IPC: G06F13/40 ,  G06F13/362 ,  G06N3/04 ,  G06F13/42 ,  G06F9/455 ,  G06N3/08 ,  G06F9/50 ,  G06F9/54 ,  G06N3/02

Abstract: There is disclosed an example of an artificial intelligence (AI) system, including: a first hardware platform; a fabric interface configured to communicatively couple the first hardware platform to a second hardware platform; a processor hosted on the first hardware platform and programmed to operate on an AI problem; and a first training accelerator, including: an accelerator hardware; a platform inter-chip link (ICL) configured to communicatively couple the first training accelerator to a second training accelerator on the first hardware platform without aid of the processor; a fabric ICL to communicatively couple the first training accelerator to a third training accelerator on a second hardware platform without aid of the processor; and a system decoder configured to operate the fabric ICL and platform ICL to share data of the accelerator hardware between the first training accelerator and second and third training accelerators without aid of the processor.

公开(公告)号：US11540355B2

公开(公告)日：2022-12-27

申请号：US16995011

申请日：2020-08-17

Applicant: Intel Corporation

Inventor： Dario Sabella ,  Ned M. Smith ,  Neal Oliver ,  Kshitij Arun Doshi ,  Suraj Prabhakaran ,  Francesc Guim Bernat ,  Miltiadis Filippou

IPC: H04W88/18 ,  H04L67/10 ,  H04W48/08 ,  H04L9/40 ,  H04W4/44 ,  H04W88/16 ,  H04L41/5019 ,  H04L67/00 ,  G06F9/455 ,  H04L67/12 ,  H04L41/083 ,  G06F8/70 ,  H04W12/00 ,  H04L67/55 ,  H04W84/12

Abstract: Various systems and methods for enhancing a distributed computing environment with multiple edge hosts and user devices, including in multi-access edge computing (MEC) network platforms and settings, are described herein. A device of a lifecycle management (LCM) proxy apparatus obtains a request, from a device application, for an application multiple context of an application. The application multiple context for the application is determined. The request from the device application for the application multiple context for the application is authorized. A device application identifier based on the request is added to the application multiple context. A created response for the device application based on the authorization of the request is transmitted to the device application. The response includes an identifier of the application multiple context.

公开(公告)号：US20220407784A1

公开(公告)日：2022-12-22

申请号：US17832903

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Kshitij Arun Doshi ,  Suraj Prabhakaran ,  Raghu Kondapalli ,  Alexander Bachmutsky

IPC: H04L41/5019 ,  H04L67/12 ,  H04L41/0806 ,  H04L41/5041 ,  H04L67/61 ,  H04L67/63

Abstract: Various systems and methods for implementing a service-level agreement (SLA) apparatus receive a request from a requester via a network interface of the gateway, the request comprising an inference model identifier that identifies a handler of the request, and a response time indicator. The response time indicator relates to a time within which the request is to be handled indicates an undefined time within which the request is to be handled. The apparatus determines a network location of a handler that is a platform or an inference model to handle the request consistent with the response time indicator, and routes the request to the handler at the network location.

公开(公告)号：US11533268B2

公开(公告)日：2022-12-20

申请号：US16958684

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Suraj Prabhakaran ,  Ignacio Astilleros Diez ,  Timothy Verrall

IPC: H04L47/50 ,  H04L67/10 ,  H04L67/60 ,  H04L67/2866 ,  H04L49/90

Abstract: An example system to schedule service requests in a network computing system using hardware queue managers includes: a gateway-level hardware queue manager in an edge gateway to schedule the service requests received from client devices in a queue; a rack-level hardware queue manager in a physical rack in communication with the edge gateway, the rack-level hardware queue manager to send a pull request to the gateway-level hardware queue manager for a first one of the service requests; and a drawer-level hardware queue manager in a drawer of the physical rack, the drawer-level hardware queue manager to send a second pull request to the rack-level hardware queue manager for the first one of the service requests, the drawer including a resource to provide a function as a service specified in the first one of the service requests.