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    Forming self-aligned multi-metal interconnects
    71.
    发明授权
    Forming self-aligned multi-metal interconnects 有权

    公开(公告)号：US11355442B2

    公开(公告)日：2022-06-07

    申请号：US16409379

    申请日：2019-05-10

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Ashim Dutta ,  Ekmini Anuja De Silva

    IPC: H01L21/768 ,  H01L23/538 ,  H01L23/532

    Abstract: An interconnect structure is provided. The interconnect structure includes first conducting lines and second conducting lines. The first conducting lines are formed of a first metallic material and include at least one individual first conducting line in contact with a first corresponding substrate conducting line. The second conducting lines are formed of a second metallic material and include at least one individual second conducting line between neighboring first conducting lines and in contact with a second corresponding substrate conducting line. The at least one individual second conducting line is separated from each of the neighboring first conducting lines by controlled distances.

    E-fuse with dielectric zipping
    72.
    发明授权
    E-fuse with dielectric zipping 有权

    公开(公告)号：US11239160B2

    公开(公告)日：2022-02-01

    申请号：US16903213

    申请日：2020-06-16

    Applicant: International Business Machines Corporation

    Inventor： Tianji Zhou ,  Saumya Sharma ,  Ashim Dutta ,  Chih-Chao Yang

    IPC: G11C16/04 ,  H01L23/525 ,  H01L23/522 ,  G11C17/16 ,  H01L23/528 ,  G11C17/18 ,  H01L23/532

    Abstract: E-fuses and techniques for fabrication thereof using dielectric zipping are provided. An e-fuse device includes: a first dielectric layer disposed on a substrate; at least one first electrode of the e-fuse device present in the first dielectric layer; a second dielectric layer disposed on the first dielectric layer; vias present in the second dielectric layer, wherein at least one of the vias is present over the at least one first electrode and has a critical dimension CDA″, wherein the vias adjacent to the at least one via having the critical dimension CDA″ each have a critical dimension of CDB″, and wherein CDB″>CDA″; a liner disposed in each of the vias; and a metal that serves as a second electrode of the e-fuse device disposed in each of the vias over the liner. A method of operating an e-fuse device is also provided.

    INTERCONNECT STRUCTURES WITH SELECTIVE CAPPING LAYER
    74.
    发明申请
    INTERCONNECT STRUCTURES WITH SELECTIVE CAPPING LAYER 有权

    公开(公告)号：US20210328137A1

    公开(公告)日：2021-10-21

    申请号：US16852997

    申请日：2020-04-20

    Applicant: International Business Machines Corporation

    Inventor： Tianji Zhou ,  Saumya Sharma ,  Ashim Dutta ,  Chih-Chao Yang

    IPC: H01L43/12 ,  H01L43/02 ,  H01L27/22

    Abstract: A method includes forming a first metallization layer containing a first metal-containing line and a second metal-containing line disposed in a first interlevel dielectric layer. The first metal-containing line includes a first conductive metal and the second metal-containing line includes a second conductive metal. The first metal-containing line and the second metal-containing line are recessed to below a top surface of the interlevel dielectric layer. A metal-containing cap protection layer is deposited in a recessed portion of the first metal-containing line and the second metal-containing line. The metal-containing cap protection layer includes a third conductive metal which is different than the first conductive metal and the second conductive metal.

    Self-aligned top via
    75.
    发明授权
    Self-aligned top via 有权

    公开(公告)号：US11133260B2

    公开(公告)日：2021-09-28

    申请号：US16685192

    申请日：2019-11-15

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Chi-Chun Liu ,  John C. Arnold ,  Dominik Metzler ,  Nelson Felix ,  Ashim Dutta

    IPC: H01L21/302 ,  H01L23/538 ,  H01L21/768 ,  H01L21/762 ,  H01L21/033 ,  H01L21/3213

    Abstract: A method of forming a self-aligned top via is provided. The method includes forming a metallization layer on a substrate, and forming a hardmask layer on the metallization layer. The method further includes forming a pair of adjacent parallel mandrels on the hardmask layer with sidewall spacers on opposite sides of each mandrel. The method further includes forming a planarization layer on the exposed portions of the hardmask layer, mandrels, and sidewall spacers, and forming an opening in the planarization layer aligned between the adjacent parallel mandrels. The method further includes forming a spacer layer in the opening, and removing portions of the spacer layer to form a pair of spacer plugs between sections of the sidewall spacers.

    Forming barrierless contact
    77.
    发明授权
    Forming barrierless contact 有权

    公开(公告)号：US11081388B2

    公开(公告)日：2021-08-03

    申请号：US16245033

    申请日：2019-01-10

    Applicant: International Business Machines Corporation

    Inventor： Kisik Choi ,  Koichi Motoyama ,  Ashim Dutta ,  Iqbal R. Saraf ,  Benjamin D. Briggs

    IPC: H01L21/768 ,  H01L23/535 ,  H01L21/02

    Abstract: Techniques for forming barrierless contacts filled with Co are provided. In one aspect, a method for forming barrierless contacts includes: forming bottom metal contacts in a first ILD; depositing a second ILD on the bottom metal contacts; forming contact vias in the second ILD landing on the bottom metal contacts; selectively forming a liner on a top surface of the second ILD and on the second ILD along sidewalls of the contact vias; filling the contact vias with a metal; and removing an excess of the metal to form the barrierless contacts whereby metal-to-metal contact is present between the barrierless contacts and the bottom metal contacts. A contact structure is also provided.

    PROCESSES FOR FORMING FULLY ALIGNED VIAS
    80.
    发明申请
    PROCESSES FOR FORMING FULLY ALIGNED VIAS 有权

    公开(公告)号：US20210104432A1

    公开(公告)日：2021-04-08

    申请号：US16592933

    申请日：2019-10-04

    Applicant: International Business Machines Corporation

    Inventor： Ekmini Anuja De Silva ,  Ashim Dutta ,  Praveen Joseph ,  Nelson Felix

    IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

    Abstract: A method of forming a semiconductor structure includes forming one or more interconnect lines, the one or more interconnect lines including trenches of a first metal material surrounded by a first interlayer dielectric layer. The method also includes forming pillars of a second metal material different than the first metal material over the one or more interconnect lines utilizing a metal on metal growth process, and forming an etch stop dielectric layer, the pillars of the second metal material shaping the etch stop dielectric layer. The method further includes forming one or more vias to the one or more interconnect lines, the one or more vias being fully aligned to the one or more interconnect lines using the etch stop dielectric layer.

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