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    Forming an MRAM device over a transistor
    71.
    发明授权
    Forming an MRAM device over a transistor 有权

    公开(公告)号：US11024670B1

    公开(公告)日：2021-06-01

    申请号：US16695601

    申请日：2019-11-26

    Applicant: International Business Machines Corporation

    Inventor： Alexander Reznicek ,  Ruilong Xie ,  Heng Wu ,  Lan Yu

    IPC: G11C11/00 ,  H01L27/22 ,  H01L43/12

    Abstract: An approach to provide a magnetoresistive random-access memory (MRAM) device that includes a first source/drain contact in a transistor in a semiconductor substrate where the source/drain contact is over a source/drain in the transistor and is surrounded by a first dielectric material. The MRAM device includes a portion of the first source/drain contact connecting to a portion of a bottom electrode of an MRAM device. Furthermore; the MRAM device includes a portion of a top electrode in the MRAM device connecting to a via, wherein the via connects to a M1 metal layer of a semiconductor chip.

    STACKED TRANSISTOR WITH SEPARATE GATE
    73.
    发明申请
    STACKED TRANSISTOR WITH SEPARATE GATE 有权

    公开(公告)号：US20210091079A1

    公开(公告)日：2021-03-25

    申请号：US16580720

    申请日：2019-09-24

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Heng Wu ,  Ruilong Xie ,  Chun Wing Yeung ,  Lan Yu

    IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165

    Abstract: Forming a first opening in a first double stacked fin and forming a second opening in a second double stacked fin, by removing a high silicon germanium layer, forming a low k spacer, removing a dummy gate, and removing portions of the low k spacer from an outer surface of the first double stacked fin, and an outer surface of the second double stacked fin. A structure including an upper fin of a double stacked fin separated from a lower fin of a double stacked fin by a low k spacer and by a p type field effect transistor work function metal layer (PFET WFM), where a horizontal lower surface of the upper fin is coplanar with a horizontal upper surface of the low k spacer and a horizontal lower surface of the low k spacer is coplanar with a horizontal upper surface of the PFET WFM.

    LEAKAGE CONTROL FOR GATE-ALL-AROUND FIELD-EFFECT TRANSISTOR DEVICES
    75.
    发明申请
    LEAKAGE CONTROL FOR GATE-ALL-AROUND FIELD-EFFECT TRANSISTOR DEVICES 审中-公开

    公开(公告)号：US20200343372A1

    公开(公告)日：2020-10-29

    申请号：US16396890

    申请日：2019-04-29

    Applicant: International Business Machines Corporation

    Inventor： Lan Yu ,  Heng Wu ,  Ruqiang Bao ,  Junli Wang ,  Dechao Guo

    IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/423 ,  H01L21/3065 ,  H01L21/762 ,  H01L29/78

    Abstract: Techniques are provided to fabricate embedded insulating layers within an active semiconductor layer of substrate to reduce leakage between field-effect transistor devices and the semiconductor substrate. For example, an epitaxial semiconductor layer is formed on a surface of a semiconductor substrate. An ion implantation process is performed to form an embedded insulation layer within the semiconductor substrate below the epitaxial semiconductor layer. A nanosheet field-effect transistor device is formed over the embedded insulation layer. The nanosheet field-effect transistor device includes active nanosheet channel layers, source/drain layers, and a high-k dielectric/metal gate structure formed around the active nanosheet channel layers. The process of forming the nanosheet field-effect transistor device includes removing the epitaxial semiconductor layer to release the active nanosheet channel layers. The embedded insulation layer isolates the high-k dielectric/metal gate structure and the source/drain layers from the semiconductor substrate.

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