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公开(公告)号:US20230165015A1
公开(公告)日:2023-05-25
申请号:US17455737
申请日:2021-11-19
发明人: John Rozen
CPC分类号: H01L27/226 , H01L43/02 , H01L43/12
摘要: A memory structure is provided. The memory structure includes a top terminal, a multi-level nonvolatile electrochemical cell, a bottom terminal, a pedestal contact in the same metal level as the bottom terminal, and a vertical conductor fully self-aligned to the multi-level nonvolatile electrochemical cell and extending vertically from the pedestal contact.
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公开(公告)号:US11568927B2
公开(公告)日:2023-01-31
申请号:US17217767
申请日:2021-03-30
发明人: John Rozen , Seyoung Kim , Paul Michael Solomon
摘要: An embodiment of the invention may include a memory structure. The memory structure may include a first terminal connected to a first contact. The memory structure may include a second terminal connected to a second contact and a third contact. The memory structure may include a multi-level nonvolatile electrochemical cell having a variable resistance channel and a programming gate. The memory structure may include the first contact and second contact connected to the variable resistance channel. The memory structure may include the third contact is connected to the programming gate. This may enable decoupled read-write operations of the device.
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公开(公告)号:US20220320426A1
公开(公告)日:2022-10-06
申请号:US17217788
申请日:2021-03-30
发明人: John Rozen
摘要: An embodiment of the invention may include a first electrode, a second electrode, and a multi-level nonvolatile electrochemical cell located between the first electrode and second electrode. The multi-level nonvolatile electrochemical cell may have a read path and a write path through the cell, where the read path and the write path are different.
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公开(公告)号:US11152214B2
公开(公告)日:2021-10-19
申请号:US15133656
申请日:2016-04-20
发明人: Takashi Ando , John Bruley , Eduard A. Cartier , Martin M. Frank , Vijay Narayanan , John Rozen
摘要: A method of forming a semiconductor device that includes forming a metal oxide material on a III-V semiconductor channel region or a germanium containing channel region; and treating the metal oxide material with an oxidation process. The method may further include depositing of a hafnium containing oxide on the metal oxide material after the oxidation process, and forming a gate conductor atop the hafnium containing oxide. The source and drain regions are on present on opposing sides of the gate structure including the metal oxide material, the hafnium containing oxide and the gate conductor.
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公开(公告)号:US10833148B2
公开(公告)日:2020-11-10
申请号:US15404860
申请日:2017-01-12
发明人: Takashi Ando , Hemanth Jagannathan , Paul C. Jamison , John Rozen
摘要: Capacitors and methods of forming the same include forming a dielectric layer on a first metal layer. The dielectric layer is oxygenated such that interstitial oxygen is implanted in the dielectric layer. A second metal layer is formed on the dielectric layer. The dielectric layer is heated to release the interstitial oxygen and to oxidize the first and second metal layers at interfaces between the dielectric layer and the first and second metal layers.
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76.
公开(公告)号:US20200083293A1
公开(公告)日:2020-03-12
申请号:US16685228
申请日:2019-11-15
发明人: Takashi Ando , Robert L. Bruce , Hiroyuki Miyazoe , John Rozen
摘要: Embodiments of the invention are directed to a vertical resistive device. A non-limiting example of the vertical resistive device includes a horizontal plate having a conductive electrode region and a filament region. An opening extends through the filament region and is defined by sidewalls of the filament such that the filament region is positioned outside of the opening. A conductive pillar is positioned within the opening and is communicatively coupled to the filament region.
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77.
公开(公告)号:US20190378876A1
公开(公告)日:2019-12-12
申请号:US16003614
申请日:2018-06-08
发明人: Takashi Ando , Robert L. Bruce , Hiroyuki Miyazoe , John Rozen
摘要: Embodiments of the invention are directed to a vertical resistive device. A non-limiting example of the vertical resistive device includes a horizontal plate having a conductive electrode region and a filament region. An opening extends through the filament region and is defined by sidewalls of the filament such that the filament region is positioned outside of the opening. A conductive pillar is positioned within the opening and is communicatively coupled to the filament region.
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公开(公告)号:US10396146B2
公开(公告)日:2019-08-27
申请号:US15801743
申请日:2017-11-02
发明人: Takashi Ando , Hemanth Jagannathan , Paul C. Jamison , John Rozen
摘要: Methods of forming capacitors include forming a dielectric layer on a first metal layer. The dielectric layer is oxygenated such that interstitial oxygen is implanted in the dielectric layer. A second metal layer is formed on the dielectric layer. The dielectric layer is heated to release the interstitial oxygen and to oxidize the first and second metal layers at interfaces between the dielectric layer and the first and second metal layers.
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公开(公告)号:US10396077B2
公开(公告)日:2019-08-27
申请号:US16012032
申请日:2018-06-19
发明人: Takashi Ando , Martin M. Frank , Renee T. Mo , Vijay Narayanan , John Rozen
IPC分类号: H01L27/092 , H01L21/8238 , H01L21/8258
摘要: Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region, the second semiconductor region being formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A nitrogen-containing layer is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.
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公开(公告)号:US10270029B2
公开(公告)日:2019-04-23
申请号:US15868506
申请日:2018-01-11
发明人: Takashi Ando , Vijay Narayanan , John Rozen
IPC分类号: H01L45/00
摘要: A resistive switching memory stack is provided. The resistive switching memory stack includes a bottom electrode, formed from one or more conductors. The resistive switching memory stack further includes an oxide layer, disposed over the bottom electrode, formed from an Atomic Layer Deposition (ALD) of one or more oxides. The resistive switching memory stack also includes a top electrode, disposed over the oxide layer, formed from the ALD of a plurality of metals into a metal layer stack. An oxygen vacancy concentration of the resistive switching memory stack is controlled by (i) a thickness of the plurality of metals forming the top electrode and (ii) a percentage of a particular one of the plurality of metals in the metal layer stack of the top electrode.
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