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公开(公告)号：US10573565B2
公开(公告)日：2020-02-25
申请号：US16273779
申请日：2019-02-12
IPC分类号： H01L21/8238 , H01L27/092 , H01L27/12 , H01L29/51 , H01L29/78 , H01L21/84 , H01L29/49 , H01L29/66 , H01L29/786
摘要： An electrical device that includes a p-type semiconductor device having a p-type work function gate structure including a first high-k gate dielectric, a first metal containing buffer layer, a first titanium nitride layer having a first thickness present on the metal containing buffer layer, and a first gate conductor contact. A mid gap semiconductor device having a mid gap gate structure including a second high-k gate dielectric, a second metal containing buffer layer, a second titanium nitride layer having a second thickness that is less than the first thickness present, and a second gate conductor contact. An n-type semiconductor device having an n-type work function gate structure including a third high-k gate dielectric present on a channel region of the n-type semiconductor device, a third metal containing buffer layer on the third high-k gate dielectric and a third gate conductor fill present atop the third metal containing buffer layer.
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2.发明申请公开(公告)号：US20200013877A1
公开(公告)日：2020-01-09
申请号：US16553912
申请日：2019-08-28
IPC分类号： H01L29/66 , H01L29/786 , H01L29/423 , H01L21/324 , H01L21/02 , H01L29/78
摘要： A method of forming a vertical fin field effect transistor device, including, forming one or more vertical fins with a hardmask cap on each vertical fin on a substrate, forming a fin liner on the one or more vertical fins and hardmask caps, forming a sacrificial liner on the fin liner, and forming a bottom spacer layer on the sacrificial liner.
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3.发明申请公开(公告)号：US20190189524A1
公开(公告)日：2019-06-20
申请号：US16273779
申请日：2019-02-12
IPC分类号： H01L21/8238 , H01L29/786 , H01L29/78 , H01L29/51 , H01L29/66 , H01L29/49 , H01L27/12 , H01L27/092 , H01L21/84
CPC分类号： H01L21/823842 , H01L21/823821 , H01L21/823878 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/4966 , H01L29/51 , H01L29/517 , H01L29/66545 , H01L29/785 , H01L29/786
摘要： An electrical device that includes a p-type semiconductor device having a p-type work function gate structure including a first high-k gate dielectric, a first metal containing buffer layer, a first titanium nitride layer having a first thickness present on the metal containing buffer layer, and a first gate conductor contact. A mid gap semiconductor device having a mid gap gate structure including a second high-k gate dielectric, a second metal containing buffer layer, a second titanium nitride layer having a second thickness that is less than the first thickness present, and a second gate conductor contact. An n-type semiconductor device having an n-type work function gate structure including a third high-k gate dielectric present on a channel region of the n-type semiconductor device, a third metal containing buffer layer on the third high-k gate dielectric and a third gate conductor fill present atop the third metal containing buffer layer.
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公开(公告)号：US10297671B2
公开(公告)日：2019-05-21
申请号：US16040978
申请日：2018-07-20
发明人： Ruqiang Bao , Hemanth Jagannathan , Paul C. Jamison , ChoongHyun Lee , Vijay Narayanan , Koji Watanabe
IPC分类号： H01L29/49 , H01L21/28 , H01L29/06 , H01L29/423 , H01L29/78 , H01L29/775 , B82Y10/00 , H01L29/66
摘要： A method is presented for forming a nanosheet structure having a uniform threshold voltage (Vt). The method includes forming a conductive barrier surrounding a nanosheet, forming a first work function conducting layer over the conductive barrier layer, and forming a conducting layer adjacent the first work function conducting layer, the conducting layer defining a first region and a second region. The method further includes forming a second work function conducting layer over the second region of the conducting layer to compensate for threshold voltage offset between the first and second regions of the conducting layer.
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5.发明授权公开(公告)号：US10283620B2
公开(公告)日：2019-05-07
申请号：US15416281
申请日：2017-01-26
IPC分类号： H01L29/66 , H01L29/786 , H01L29/423 , H01L21/324 , H01L21/02 , H01L29/78
摘要： A method of forming a vertical fin field effect transistor device, including, forming one or more vertical fins with a hardmask cap on each vertical fin on a substrate, forming a fin liner on the one or more vertical fins and hardmask caps, forming a sacrificial liner on the fin liner, and forming a bottom spacer layer on the sacrificial liner.
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6.发明授权公开(公告)号：US10002791B1
公开(公告)日：2018-06-19
申请号：US15481012
申请日：2017-04-06
IPC分类号： H01L21/28 , H01L21/8234 , H01L27/088 , H01L27/092 , H01L21/8238 , H01L29/49 , H01L29/66
CPC分类号： H01L21/82345 , H01L21/823487 , H01L21/823821 , H01L21/823842 , H01L21/823885 , H01L27/088 , H01L27/092 , H01L27/0924 , H01L29/4958 , H01L29/4966 , H01L29/66545 , H01L29/785
摘要： A method is presented for forming a device having multiple field effect transistors (FETs) with each FET having a different work function. In particular, the method includes forming multiple microchips in which each FET has a different threshold voltage (Vt) or work-function. In one embodiment, four FETs are formed over a semiconductor substrate. Each FET has a source, drain and a gate electrode. Each gate electrode is processed independently to provide a substantially different threshold voltage.
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公开(公告)号：US09653537B1
公开(公告)日：2017-05-16
申请号：US15275846
申请日：2016-09-26
IPC分类号： H01L29/06 , H01L29/41 , H01L29/43 , H01L29/786 , H01L29/423
CPC分类号： H01L21/28088 , H01L21/28556 , H01L29/0665 , H01L29/0673 , H01L29/401 , H01L29/42392 , H01L29/47 , H01L29/4966 , H01L29/66439 , H01L29/775 , H01L29/78642
摘要： Embodiments are directed to a method of forming a semiconductor device and resulting structures for controlling a threshold voltage on a nanosheet-based transistor. A nanosheet stack is formed over a substrate. The nanosheet stack includes a first nanosheet vertically stacked over a second nanosheet. A tri-layer gate metal stack is formed on each nanosheet. The tri-layer gate metal stack includes an inner nitride layer formed on a surface of each nanosheet, a doped transition metal layer formed on each inner nitride layer, and an outer nitride layer formed on each doped transition metal layer.
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公开(公告)号：US20160315166A1
公开(公告)日：2016-10-27
申请号：US15200141
申请日：2016-07-01
CPC分类号： H01L21/283 , H01L21/28158 , H01L21/28202 , H01L21/28211 , H01L29/4958 , H01L29/4966 , H01L29/513 , H01L29/518 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66795 , H01L29/7833 , H01L29/785
摘要： A stratified gate dielectric stack includes a first high dielectric constant (high-k) gate dielectric comprising a first high-k dielectric material, a band-gap-disrupting dielectric comprising a dielectric material having a different band gap than the first high-k dielectric material, and a second high-k gate dielectric comprising a second high-k dielectric material. The band-gap-disrupting dielectric includes at least one contiguous atomic layer of the dielectric material. Thus, the stratified gate dielectric stack includes a first atomic interface between the first high-k gate dielectric and the band-gap-disrupting dielectric, and a second atomic interface between the second high-k gate dielectric and the band-gap-disrupting dielectric that is spaced from the first atomic interface by at least one continuous atomic layer of the dielectric material of the band-gap-disrupting dielectric. The insertion of the band-gap disrupting dielectric results in lower gate leakage without resulting in any substantial changes in the threshold voltage characteristics and effective oxide thickness.
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9.发明授权Fin field effect transistors having a nitride containing spacer to reduce lateral growth of epitaxially deposited semiconductor materials 有权翅片场效应晶体管具有含氮化物的间隔物以减少外延沉积的半导体材料的横向生长公开(公告)号：US08802513B2
公开(公告)日：2014-08-12
申请号：US13666386
申请日：2012-11-01
IPC分类号： H01L21/336 , H01L23/58 , H01L29/06 , H01L29/78
CPC分类号： H01L27/0886 , H01L21/823431 , H01L29/66553 , H01L29/66795 , H01L29/785 , H01L2924/0002 , H01L2924/00
摘要： A fin field effect transistor including a plurality of fin structures on a substrate, and a shared gate structure on a channel portion of the plurality of fin structures. The fin field effect transistor further includes an epitaxial semiconductor material having a first portion between adjacent fin structures in the plurality of fin structures and a second portion present on outermost sidewalls of end fin structures of the plurality of fin structures. The epitaxial semiconductor material provides a source region and at drain region to each fin structure of the plurality of fin structures. A nitride containing spacer is present on the outermost sidewalls of the second portion of the epitaxial semiconductor material.
摘要翻译： 一种鳍状场效应晶体管，包括在衬底上的多个翅片结构，以及在所述多个翅片结构的通道部分上的共享栅极结构。 鳍状场效应晶体管还包括外延半导体材料，该外延半导体材料具有在多个翅片结构中的相邻鳍结构之间的第一部分和存在于多个翅片结构的端鳍结构的最外侧壁上的第二部分。 外延半导体材料在多个鳍结构的每个鳍结构处提供源极区域和漏极区域。 含氮化物的间隔物存在于外延半导体材料的第二部分的最外侧壁上。
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公开(公告)号：US10978551B2
公开(公告)日：2021-04-13
申请号：US15832250
申请日：2017-12-05
IPC分类号： H01L49/02 , H01L23/522 , H01L21/02 , H01L21/285 , H01L23/48
摘要： A method for forming a metal-insulator-metal (MIM) capacitor on a semiconductor substrate is presented. The method includes forming a first electrode defining columnar grains, forming a dielectric layer over the first electrode, and forming a second electrode over the dielectric layer. The first and second electrodes can be titanium nitride (TiN) electrodes. The dielectric layer can include one of hafnium oxide and zirconium oxide deposited by atomic layer deposition (ALD). The ALD results in deposition of high-k films in grain boundaries of the first electrode.
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