公开(公告)号：US07400549B2

公开(公告)日：2008-07-15

申请号：US11116597

申请日：2005-04-28

Applicant: Jin-Man Han ,  Aaron Yip

Inventor： Jin-Man Han ,  Aaron Yip

IPC: G11C8/00

CPC classification number: G11C8/08 ,  G06F12/0246 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3418 ,  G11C16/3427 ,  G11C29/76 ,  G11C29/82 ,  Y02D10/13

Abstract: A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability. Each of the reallocation blocks that contain the reallocated pages from the desired memory block are coupled to a wordline driver. These wordline drivers have a subset of the global wordlines as inputs. The desired wordline driver is selected by an appropriate select signal from a block decoder and an indication on an appropriate global wordline. This causes the wordline driver to generate a local wordline to the desired block with the reallocated page to be accessed.

Abstract translation: 非易失性存储器件具有将特定存储器块的页面重新分配给其他块，以便增加减少的干扰并增加可靠性。 包含来自期望的存储器块的重新分配的页面的每个重新分配块被耦合到字线驱动器。 这些字线驱动器具有全局字线的一部分作为输入。 期望的字线驱动器通过来自块解码器的适当选择信号和适当的全局字线上的指示来选择。 这将导致字线驱动程序在要重新分配的页面访问期望块时生成本地字线。

公开(公告)号：US20080055988A1

公开(公告)日：2008-03-06

申请号：US11511451

申请日：2006-08-29

Applicant: Jin-Man Han

Inventor： Jin-Man Han

IPC: G11C11/34

CPC classification number: G11C8/20 ,  G06F11/1068 ,  G11C8/10 ,  G11C29/808 ,  G11C2029/0411

Abstract: A method, apparatus and system are described which provide a memory device having an array of cells which may be selectively designated for either error correction code use or redundancy cell use.

Abstract translation: 描述了提供具有可以选择性地指定用于纠错码使用或冗余电池使用的单元阵列的存储器件的方法，装置和系统。

公开(公告)号：US20080031041A1

公开(公告)日：2008-02-07

申请号：US11500153

申请日：2006-08-07

Applicant: Jin-Man Han

Inventor： Jin-Man Han

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5641

Abstract: A non-volatile memory array with both single level cells and multilevel cells. The single level and multilevel cells, in one embodiment, are alternated either along each bit line. An alternate embodiment alternates the single and multilevel cells along both the bit lines and the word lines so that no single level cell is adjacent to another single level cell in either the word line or the bit line directions.

Abstract translation: 具有单级单元和多级单元的非易失性存储器阵列。 在一个实施例中，单电平和多电平电池沿着每个位线交替。 一个替代实施例沿着位线和字线交替单电层和多电平单元，使得没有单层单元与字线或位线方向上的另一单级单元相邻。

公开(公告)号：US07196930B2

公开(公告)日：2007-03-27

申请号：US11115681

申请日：2005-04-27

Applicant: Jin-Man Han ,  Benjamin Louie

Inventor： Jin-Man Han ,  Benjamin Louie

IPC: G11C11/34

CPC classification number: G11C16/12 ,  G11C16/0483 ,  G11C16/3427

Abstract: The method for reducing program disturb in a flash memory array biases a selected wordline at a programming voltage. One of the unselected wordlines, closer to array ground than the selected wordline, is biased at a voltage that is less than Vpass. The memory cells on this unselected wordline that are biased at this voltage block the gate induced drain leakage from the cells further up in the array. The remaining unselected wordlines are biased at Vpass. In another embodiment, a second source select gate line is added to the array. The source select gate line that is closest to the wordlines is biased at the voltage that is less than Vpass in order to block the gate induced drain leakage from the array.

Abstract translation: 用于减少闪速存储器阵列中的编程干扰的方法在编程电压下偏置所选择的字线。 未选择的字线之一，比所选择的字线更接近阵列地，被偏置在小于V 的电压。 在这个未被选择的字线上被偏置在该电压下的存储器单元阻挡栅极引起的漏极从阵列中的细胞进一步上升。 剩余的未选择的字线偏向V 。 在另一个实施例中，第二源选择栅极线被添加到阵列。 最靠近字线的源选择栅极线被偏置在小于V 的电压，以便阻挡来自阵列的栅感应漏极泄漏。

公开(公告)号：US20060245270A1

公开(公告)日：2006-11-02

申请号：US11115489

申请日：2005-04-27

Applicant: Benjamin Louie ,  Yunqiu Wan ,  Aaron Yip ,  Jin-Man Han

Inventor： Benjamin Louie ,  Yunqiu Wan ,  Aaron Yip ,  Jin-Man Han

IPC: G11C7/10

CPC classification number: G11C7/1042 ,  G11C7/1051 ,  G11C16/26 ,  G11C2207/2245

Abstract: A non-volatile memory is described that utilizes a cache read mode of operation, where a next page of memory is being read/sensed from the memory array by the sense amplifiers while a previously read page of memory is being read from the memory I/O buffer, wherein the next page is user selected. This random cache read mode allows for a memory with a random page read capability, in which the address of the next page of data to be read is user selectable, which benefits from the low latency of a cache read mode of operation due to concurrent data sensing and data I/O.

Abstract translation: 描述了利用高速缓存读取操作模式的非易失性存储器，其中由读出放大器从存储器阵列读取/感测存储器的下一页，同时从存储器I / O缓冲器，其中下一页是用户选择的。 这种随机高速缓存读取模式允许具有随机页面读取功能的存储器，其中要读取的下一页数据的地址是用户可选择的，这受益于由于并发数据而导致的高速缓存读取操作模式的低等待时间 感测和数据I / O。

公开(公告)号：US20060245252A1

公开(公告)日：2006-11-02

申请号：US11115681

申请日：2005-04-27

Applicant: Jin-Man Han ,  Benjamin Louie

Inventor： Jin-Man Han ,  Benjamin Louie

IPC: G11C16/04

CPC classification number: G11C16/12 ,  G11C16/0483 ,  G11C16/3427

Abstract: The method for reducing program disturb in a flash memory array biases a selected wordline at a programming voltage. One of the unselected wordlines, closer to array ground than the selected wordline, is biased at a voltage that is less than Vpass. The memory cells on this unselected wordline that are biased at this voltage block the gate induced drain leakage from the cells further up in the array. The remaining unselected wordlines are biased at Vpass. In another embodiment, a second source select gate line is added to the array. The source select gate line that is closest to the wordlines is biased at the voltage that is less than Vpass in order to block the gate induced drain leakage from the array.

Abstract translation: 用于减少闪速存储器阵列中的编程干扰的方法在编程电压下偏置所选择的字线。 未选择的字线之一，比所选择的字线更接近阵列地，被偏置在小于V 的电压。 在这个未被选择的字线上被偏置在该电压下的存储器单元阻挡栅极引起的漏极从阵列中的细胞进一步上升。 剩余的未选择的字线偏向V 。 在另一个实施例中，第二源选择栅极线被添加到阵列。 最靠近字线的源选择栅极线被偏置在小于V 的电压上，以便阻挡来自阵列的栅感应漏极泄漏。

公开(公告)号：US06903987B2

公开(公告)日：2005-06-07

申请号：US10211766

申请日：2002-08-01

Applicant: Sei-Seung Yoon ,  Jin-Man Han ,  Seong-Ook Jung

Inventor： Sei-Seung Yoon ,  Jin-Man Han ,  Seong-Ook Jung

IPC: G11C11/00 ,  G11C11/39 ,  H01L21/8244 ,  H01L27/11 ,  H01L31/111

CPC classification number: H01L27/11 ,  G11C11/39

Abstract: A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell is disclosed herein. The sensing circuit includes a bit line to receive the data signal, a first pre-charge device coupled to the bit line and configured to pre-charge the bit line, a device for providing a bias coupled to the bit line and configured to provide a bias to the bit line, and a reference node configured to be at least one pre-determined level. In one embodiment the pre-determined level is equal to a low potential such as ground and in another embodiment equal to a high potential such as VDD. One or more switching devices allows for the activation or deactivation of the pre-charge device allowing to pre-charge the bit line to a certain potential and the sensing circuit quickly and accurately determines whether a logical state of ‘1’ or ‘0’ is being applied to the bit line.

Abstract translation: 本文公开了一种包括用于解析由存储器单元产生的数据信号的读出放大器的感测电路。 感测电路包括用于接收数据信号的位线，耦合到位线并被配置为对位线预充电的第一预充电器件，用于提供耦合到位线的偏置并被配置为提供 偏置到位线，以及被配置为至少一个预定电平的参考节点。 在一个实施例中，预定电平等于诸如地电位的低电位，而在另一实施例中等于诸如V DD的高电位。 一个或多个开关装置允许激活或去激活预充电装置，允许将位线预充电到特定电位，感测电路快速而准确地确定逻辑状态“1”或“0”是否为 应用于位线。

公开(公告)号：US06845037B1

公开(公告)日：2005-01-18

申请号：US10634268

申请日：2003-08-05

Applicant: Jin-Man Han

Inventor： Jin-Man Han

IPC: G11C7/14 ,  G11C11/39 ,  G11C11/00

CPC classification number: G11C7/14 ,  G11C11/39

Abstract: A reference cell produces a voltage rise on a bit line that is proportional to, and preferably half of, the voltage rise on another bit line produced by a TCCT based memory cell in an “on” state. The reference cell includes an NDR device, a gate-like device disposed adjacent to the NDR device, a first resistive element coupled between the NDR device and the bit line, and a second resistive element coupled between a sink and the bit line. Resistances of the first and second resistive elements are about equal and about twice as much as the resistance of a pass transistor of the a TCCT based memory cell.

Abstract translation: 参考单元产生位线上的电压上升，该位线与由处于“开”状态的基于TCCT的存储单元产生的另一位线上的电压上升成比例，最好是一半。 参考单元包括NDR器件，邻近NDR器件设置的栅极状器件，耦合在NDR器件和位线之间的第一电阻元件以及耦合在漏极与位线之间的第二电阻元件。 第一和第二电阻元件的电阻大约相当于基于TCCT的存储单元的通过晶体管的电阻的两倍。

公开(公告)号：US06611452B1

公开(公告)日：2003-08-26

申请号：US10117930

申请日：2002-04-05

Applicant: Jin-Man Han

Inventor： Jin-Man Han

IPC: G11C1100

CPC classification number: G11C7/14 ,  G11C11/39

Abstract: A reference cell produces a voltage rise on a bit line that is proportional to, and preferably half of, the voltage rise on another bit line produced by a TCCT based memory cell in an “on” state. The reference cell includes an NDR device, a gate-like device disposed adjacent to the NDR device, a first resistive element coupled between the NDR device and the bit line, and a second resistive element coupled between a sink and the bit line. Resistances of the first and second resistive elements are about equal and about twice as much as the resistance of a pass transistor of the a TCCT based memory cell.

Abstract translation: 参考单元产生位线上的电压上升，该位线与由处于“开”状态的基于TCCT的存储单元产生的另一位线上的电压上升成比例，最好是一半。 参考单元包括NDR器件，邻近NDR器件设置的栅极状器件，耦合在NDR器件和位线之间的第一电阻元件以及耦合在漏极与位线之间的第二电阻元件。 第一和第二电阻元件的电阻大约相当于基于TCCT的存储单元的通过晶体管的电阻的两倍。