公开(公告)号：US08994119B2

公开(公告)日：2015-03-31

申请号：US13520618

申请日：2012-04-11

Applicant: Huaxiang Yin ,  Zuozhen Fu ,  Qiuxia Xu ,  Chao Zhao ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Zuozhen Fu ,  Qiuxia Xu ,  Chao Zhao ,  Dapeng Chen

IPC: H01L27/088 ,  H01L21/8236 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L21/823807 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7845

Abstract: The present invention discloses a semiconductor device, comprising substrates, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, a plurality of source and drain regions in the substrate on both sides of each gate spacer structure, the plurality of gate spacer structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, wherein each of the first gate stack structures comprises a first gate insulating layer, a first work function metal layer, a second work function metal diffusion blocking layer, and a gate filling layer; Each of the second gate stack structures comprises a second gate insulating layer, a first work function metal layer, a second work function metal layer, and a gate filling layer, characterized in that the first work function metal layer has a first stress, and the gate filling layer has a second stress. Two metal gate layers of different types and/or intensity of stress are formed, respectively, thus different stresses are applied to the channel regions of different MOSFETs effectively and accurately, the device carrier mobility is enhanced simply and efficiently, and the device performance is also enhanced.

Abstract translation: 本发明公开了一种半导体器件，包括衬底，衬底上的多个栅极堆叠结构，在每个栅极堆叠结构的两侧上的多个栅极间隔结构，在衬底的两侧的多个源极和漏极区域 每个栅极间隔结构，所述多个栅极间隔结构包括多个第一栅极堆叠结构和多个第二栅极堆叠结构，其中所述第一栅极堆叠结构中的每一个包括第一栅极绝缘层，第一功函数金属层， 第二功函数金属扩散阻挡层和栅极填充层; 每个第二栅极堆叠结构包括第二栅极绝缘层，第一功函数金属层，第二功函数金属层和栅极填充层，其特征在于，第一功函数金属层具有第一应力，并且 栅极填充层具有第二应力。 形成不同类型和/或应力强度的两个金属栅极层，从而有效且准确地对不同MOSFET的沟道区域施加不同的应力，简化高效地提高器件载流子迁移率，器件性能也 增强。

公开(公告)号：US08686534B2

公开(公告)日：2014-04-01

申请号：US13145301

申请日：2011-04-22

Applicant: Huicai Zhong ,  Chao Zhao ,  Qingqing Liang

Inventor： Huicai Zhong ,  Chao Zhao ,  Qingqing Liang

IPC: H01L29/00 ,  H01L21/76

CPC classification number: H01L21/76224 ,  H01L21/76232 ,  H01L29/02

Abstract: A trench isolation structure and a method of forming the same are provided. The trench isolation structure includes: a semiconductor substrate, and trenches formed in the semiconductor substrate and filled with a dielectric layer, where the material of the dielectric layer is a crystalline material. By using the present invention, the size of the divot can be reduced, and device performances can be improved.

Abstract translation: 提供了沟槽隔离结构及其形成方法。 沟槽隔离结构包括：半导体衬底和形成在半导体衬底中并填充有电介质层的沟槽，其中电介质层的材料是结晶材料。 通过使用本发明，可以减小纹路的尺寸，并且可以提高器件性能。

公开(公告)号：US08647987B2

公开(公告)日：2014-02-11

申请号：US13698283

申请日：2012-06-12

Applicant: Tao Yang ,  Chao Zhao ,  Junfeng Li

Inventor： Tao Yang ,  Chao Zhao ,  Junfeng Li

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/311

CPC classification number: H01L21/30625 ,  H01L21/31053 ,  H01L21/31056 ,  H01L22/26 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention provides a method for improving uniformity of chemical-mechanical planarization process, comprising the steps of: forming features on a substrate; forming a first dielectric isolation layer between the features; planarizing the first dielectric isolation layer until the features are exposed, causing the first dielectric isolation layer between the features to have a recess depth; forming a second dielectric isolation layer on the features and the first dielectric isolation layer, whereby reducing the difference in height between the second dielectric isolation layer between the features and the second dielectric isolation layer on the top of the features; planarizing the second dielectric isolation layer until the features are exposed. According to the method for improving uniformity of chemical-mechanical planarization process of the invention, a dielectric isolation layer is formed again after grinding the dielectric isolation layer on the top of the features, such that the difference in height between the dielectric layer between the features and the dielectric layer on the top of the features is effectively reduced, and the recess of the features is compensated, the within-in-die uniformity is effectively improved.

Abstract translation: 本发明提供了一种改善化学机械平面化工艺的均匀性的方法，包括以下步骤：在基底上形成特征; 在所述特征之间形成第一绝缘隔离层; 平面化第一介电隔离层直到特征被暴露，使得特征之间的第一介电隔离层具有凹陷深度; 在特征和第一介电隔离层上形成第二绝缘隔离层，从而减小特征之间的第二介电隔离层与特征顶部的第二介电隔离层之间的高度差; 平坦化第二介电隔离层，直到特征被暴露。 根据本发明的化学机械平面化工艺的均匀性提高方法，在研磨特征顶部的介电隔离层之后再次形成介电隔离层，使得介电层之间的高度差 并且功能顶部的电介质层被有效地减少，并且特征的凹部得到补偿，从而有效地提高了模内均匀性。

公开(公告)号：US20140001646A1

公开(公告)日：2014-01-02

申请号：US13697372

申请日：2012-07-31

Applicant: Lijun Dong ,  Chao Zhao

Inventor： Lijun Dong ,  Chao Zhao

IPC: H01L21/768 ,  H01L23/498

CPC classification number: H01L21/76802 ,  H01L21/486 ,  H01L23/147 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A solid hole array and a manufacture method thereof are provided. The method for manufacturing the solid hole array comprises: forming a top hole array base and a bottom hole array base on a top surface and a bottom surface of a substrate respectively; forming a front hole in the top hole array base; forming a top protection layer on the substrate with the top hole array base, and forming a bottom protection layer on the bottom hole array base; forming a rear window in the bottom hole array base and the bottom protection layer; and etching through the substrate by alkali corrosion to connect the front hole with the rear window. In addition, the present disclosure also provides a solid hole array. Using the method of the present disclosure, the intensity of the front film is enhanced, the process steps are simplified, the cost is decreased, and a large scale manufacture is more likely.

Abstract translation: 提供了一种固体孔阵列及其制造方法。 固体孔阵列的制造方法包括：分别在衬底的顶表面和底表面上形成顶孔阵列基底和底孔阵列基底; 在顶孔阵列基底中形成前孔; 在顶孔阵列基底上形成顶层保护层，在底孔阵列基底上形成底层保护层; 在底孔阵列基底和底部保护层中形成后窗; 并通过碱腐蚀蚀刻基板，将前孔与后窗连接起来。 此外，本公开还提供了一种固体孔阵列。 利用本公开的方法，提高了前膜的强度，简化了工艺步骤，降低了成本，并且更有可能进行大规模制造。

公开(公告)号：US08557677B2

公开(公告)日：2013-10-15

申请号：US13120792

申请日：2011-02-17

Applicant: Qingqing Liang ,  Huicai Zhong ,  Chao Zhao ,  Huilong Zhu

Inventor： Qingqing Liang ,  Huicai Zhong ,  Chao Zhao ,  Huilong Zhu

IPC: H01L21/30

CPC classification number: H01L25/50 ,  H01L21/6835 ,  H01L23/481 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A stack-type semiconductor device includes a semiconductor substrate; and a plurality of wafer assemblies arranged in various levels on the semiconductor substrate, in which the wafer assembly in each level includes an active part and an interconnect part, and the active part and the interconnect part each have conductive through vias, wherein the conductive through vias in the active part are aligned with the conductive through vias in the interconnect part in a vertical direction, so that the active part in each level is electrically coupled with the active part in the previous level and/or the active part in the next level by the conductive through vias. Such a stack-type semiconductor device and the related methods can be applied in a process after the FEOL or in a semiconductor chip packaging process and provide a 3-dimensional semiconductor device of high integration and high reliability.

Abstract translation: 堆叠型半导体器件包括半导体衬底; 以及在所述半导体衬底上以各种级别布置的多个晶片组件，其中每个级中的所述晶片组件包括有源部分和互连部分，并且所述有源部分和所述互连部件各自具有导电通孔，其中所述导电通孔 有源部分中的通孔在垂直方向上与互连部分中的导电通孔对准，使得每个电平中的有源部分与先前电平中的有源部分和/或下一级的有源部分电耦合 通过导电通孔。 这种叠层型半导体器件及相关方法可以在FEOL之后的工艺中或半导体芯片封装工艺中应用，并提供高集成度和高​​可靠性的三维半导体器件。

公开(公告)号：US08455323B2

公开(公告)日：2013-06-04

申请号：US13201125

申请日：2011-02-25

Applicant: Huicai Zhong ,  Qingqing Liang ,  Chao Zhao

Inventor： Huicai Zhong ,  Qingqing Liang ,  Chao Zhao

IPC: H01L21/336

CPC classification number: H01L21/3221

Abstract: There is provided a method for manufacturing a semiconductor wafer, comprising: performing heating so that metals dissolve into semiconductors of the wafer to form a semiconductor-metal compound; and performing cooling so that the formed semiconductor-metal compound retrogradely melt to form a mixture of the metals and the semiconductors. According to embodiments of the present invention, it is possible to achieve wafers of a high purity applicable to the semiconductor manufacture.

Abstract translation: 提供了一种制造半导体晶片的方法，包括：进行加热，使得金属溶解到晶片的半导体中以形成半导体 - 金属化合物; 并进行冷却，使得所形成的半导体 - 金属化合物逆向熔融以形成金属和半导体的混合物。 根据本发明的实施例，可以实现适用于半导体制造的高纯度晶片。

公开(公告)号：US08409986B2

公开(公告)日：2013-04-02

申请号：US13377889

申请日：2011-04-20

Applicant: Tao Yang ,  Chao Zhao ,  Junfong Li

Inventor： Tao Yang ,  Chao Zhao ,  Junfong Li

IPC: H01L21/768

CPC classification number: H01L21/7684 ,  H01L21/3212 ,  H01L21/32135

Abstract: A method for improving the within die uniformity of the metal plug CMP process in the gate last route is provided. Before performing the CMP process for forming the metal plug, a metal etching process is applied, so that the step height between the metal layers in the contact hole area and the non-contact hole area is greatly reduced. Therefore, the relatively small step height will exert a significantly less effect on the following CMP process, so that the step height will be limitedly transferred to the top of metal plug after finishing CMP process. In this way, the recess on top of the metal plug is largely reduced, so that a flat top of the metal plug is obtained, and within die uniformity and electrical properties the device are improved.

Abstract translation: 提供了一种用于提高门最后路线中的金属塞CMP工艺的模内均匀性的方法。 在进行用于形成金属插塞的CMP处理之前，应用金属蚀刻工艺，使得接触孔区域中的金属层与非接触孔区域之间的台阶高度大大降低。 因此，相对较小的台阶高度将对下列CMP工艺产生显着影响较小，因此在完成CMP工艺后，台阶高度将有限地转移到金属插头的顶部。 以这种方式，金属插头顶部的凹槽大大减小，从而获得金属插头的平坦的顶部，并且在模具的均匀性和电气特性中改进了该装置。

公开(公告)号：US20120322172A1

公开(公告)日：2012-12-20

申请号：US13499288

申请日：2011-11-29

Applicant: Tao Yang ,  Chao Zhao ,  Junfeng Li ,  Jiang Yan ,  Dapeng Chen

Inventor： Tao Yang ,  Chao Zhao ,  Junfeng Li ,  Jiang Yan ,  Dapeng Chen

IPC: H01L21/66

CPC classification number: H01L22/12 ,  H01L29/66545

Abstract: The present invention discloses a method for monitoring the removal of a polycrystalline silicon dummy gate, comprising the steps of: forming a polycrystalline silicon dummy gate structure on a surface of a wafer; determining a measurement target and an error range of mass of the wafer; and measuring the mass of the wafer by a mass measurement tool after polycrystalline silicon dummy gate removal to determine whether the polycrystalline silicon dummy gate has been completely removed. According to the measurement method of the present invention, the full wafer may be quickly and accurately measured without requiring a specific test structure, to effectively monitor and determine whether the polysilicon dummy gate is thoroughly removed, meanwhile said measurement method gives feedback directly, quickly and accurately without causing any damage to the wafer.

Abstract translation: 本发明公开了一种用于监测多晶硅虚拟栅极去除的方法，包括以下步骤：在晶片的表面上形成多晶硅虚拟栅极结构; 确定晶片的测量目标和质量的误差范围; 以及通过质量测量工具在多晶硅虚拟栅极去除之后测量晶片的质量，以确定多晶硅虚拟栅极是否被完全去除。 根据本发明的测量方法，可以快速且准确地测量全晶片而不需要特定的测试结构，以有效地监测和确定多晶硅虚拟栅极是否被彻底去除，同时所述测量方法直接，快速地给出反馈， 准确地不会对晶片造成任何损坏。

公开(公告)号：US20120319215A1

公开(公告)日：2012-12-20

申请号：US13497744

申请日：2011-11-29

Applicant: Guilei Wang ,  Chunlong Li ,  Chao Zhao

Inventor： Guilei Wang ,  Chunlong Li ,  Chao Zhao

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/1054 ,  H01L29/66651 ,  H01L29/7833

Abstract: The present invention discloses a semiconductor device and method of manufacturing the same, comprising: forming an insulating isolation layer on a substrate; forming an insulating isolation layer trench in the insulating isolation layer; forming an active region layer in the insulating isolation layer trench; and forming a semiconductor device structure in and above the active region layer, wherein the carrier mobility of the active region layer is higher than that of the substrate. In accordance with the semiconductor device and the manufacturing method thereof in the present invention, an active region formed of a material different from that of the substrate is used, the carrier mobility in the channel region is enhanced, thereby the device response speed is substantially improved and the device performance is enhanced greatly. Furthermore, unlike the existing STI manufacturing process, in the present invention a STI is formed first, and then filling is performed to form an active region, to avoid the problem of generation of holes in the STI and improve the device reliability.

Abstract translation: 本发明公开了一种半导体器件及其制造方法，包括：在衬底上形成绝缘隔离层; 在绝缘隔离层中形成绝缘隔离层沟槽; 在绝缘隔离层沟槽中形成有源区; 以及在所述有源区域层中和之上形成半导体器件结构，其中所述有源区域层的载流子迁移率高于所述衬底的载流子迁移率。 根据本发明的半导体器件及其制造方法，使用由与衬底不同的材料形成的有源区域，增加沟道区域中的载流子迁移率，从而显着提高器件响应速度 设备性能大大提升。 此外，与现有的STI制造方法不同，在本发明中，首先形成STI，然后进行填充以形成有源区，以避免在STI中产生孔的问题，并提高器件的可靠性。

公开(公告)号：US08252689B2

公开(公告)日：2012-08-28

申请号：US13142736

申请日：2011-04-12

Applicant: Tao Yang ,  Jinbiao Liu ,  Xiaobin He ,  Chao Zhao ,  Dapeng Chen

Inventor： Tao Yang ,  Jinbiao Liu ,  Xiaobin He ,  Chao Zhao ,  Dapeng Chen

IPC: H01L21/302

CPC classification number: H01L21/31053 ,  H01L21/31155 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/78

Abstract: The present invention provides a chemical-mechanical planarization method. The chemical-mechanical planarization method includes: providing a substrate including a gate and source/drain regions on the sides of the gate, the gate and the source/drain regions being overlay by an insulating layer, and the insulating layer including a protruding part above the gate and a recessed part above a surface of the substrate between gates; selectively doping the insulating layer such that only the protruding part is doped; and performing CMP on the substrate after doping, to remove the protruding part and planarize the surface of the substrate. By selectively doping the insulating layer, the method makes only the protruding part of the insulating layer doped, enhancing the corrosive attacks on the material of the protruding part by the slurry in the CMP, and increasing the removal rate of the material of the protruding part by the CMP.

Abstract translation: 本发明提供了一种化学机械平面化方法。 化学机械平面化方法包括：在栅极的侧面设置包括栅极和源极/漏极区域的衬底，栅极和源极/漏极区域被绝缘层覆盖，并且绝缘层包括在上方的突出部分 栅极和位于栅极之间的衬底表面上方的凹陷部分; 选择性地掺杂绝缘层，使得只有突出部分被掺杂; 并且在掺杂之后在衬底上执行CMP以去除突出部分并使衬底的表面平坦化。 通过选择性地掺杂绝缘层，该方法仅使掺杂的绝缘层的突出部分增加了CMP中的浆料对突出部分的材料的腐蚀攻击，并且增加了突出部分的材料的去除速率 由CMP。