公开(公告)号：US20060202258A1

公开(公告)日：2006-09-14

申请号：US11435456

申请日：2006-05-16

申请人： Nima Mokhlesi ,  Jeffrey Lutze

发明人： Nima Mokhlesi ,  Jeffrey Lutze

IPC分类号： H01L29/788

CPC分类号： H01L27/11 ,  H01L21/28273 ,  H01L21/823437 ,  H01L27/1104 ,  H01L27/115 ,  Y10S257/903

摘要： Various techniques are described which utilize multiple poly-silicon layers in the design and fabrication of various logic elements that are used in semiconductor devices. According to a specific implementation of the present invention, logic gate cell sizes and memory array cell sizes may be reduced by fabricating various transistor gates using multiple poly-silicon layers. The techniques of the present invention of using multiple layers of poly-silicon to form transistor gates of logic elements provides extra degrees of freedom in fine tuning transistor parameters such as, for example, oxide thickness, threshold voltage, maximum allowed gate voltage, etc.

摘要翻译： 描述了在半导体器件中使用的各种逻辑元件的设计和制造中利用多个多晶硅层的各种技术。 根据本发明的具体实现，可以通过使用多个多晶硅层制造各种晶体管栅极来减小逻辑门单元尺寸和存储器阵列单元尺寸。 使用多层多晶硅形成逻辑元件的晶体管栅极的本发明的技术在微调晶体管参数例如氧化物厚度，阈值电压，最大允许栅极电压等中提供了额外的自由度。

公开(公告)号：US07064034B2

公开(公告)日：2006-06-20

申请号：US10211433

申请日：2002-08-02

申请人： Nima Mokhlesi ,  Jeffrey Lutze

发明人： Nima Mokhlesi ,  Jeffrey Lutze

IPC分类号： H01L21/8234 ,  H01L21/8236

CPC分类号： H01L27/11 ,  H01L21/28273 ,  H01L21/823437 ,  H01L27/1104 ,  H01L27/115 ,  Y10S257/903

摘要： Various techniques are described which utilize multiple poly-silicon layers in the design and fabrication of various logic elements that are used in semiconductor devices. According to a specific implementation of the present invention, logic gate cell sizes and memory array cell sizes may be reduced by fabricating various transistor gates using multiple poly-silicon layers. The techniques of the present invention of using multiple layers of poly-silicon to form transistor gates of logic elements provides extra degrees of freedom in fine tuning transistor parameters such as, for example, oxide thickness, threshold voltage, maximum allowed gate voltage, etc.

公开(公告)号：US06448122B1

公开(公告)日：2002-09-10

申请号：US09598759

申请日：2000-06-22

申请人： Emmanuel de Muizon ,  Jeffrey Lutze

发明人： Emmanuel de Muizon ,  Jeffrey Lutze

IPC分类号： H01L218238

CPC分类号： H01L21/823418 ,  H01L21/823468

摘要： An integrated circuit manufacturing process selectively blocks silicide formation during the fabrication of I/O devices to enhance their ESD performance while not impacting the performance of core devices. In an example embodiment, a spacer dielectric covers the MOS structure so that the gate may be protected from process degradation. The spacer dielectric is masked to define silicidation blocking regions and silicidation accepting regions. Spacer dielectric is removed in regions where silicidation is to be accepted. Silicidation blocking regions protect transistor devices from subsequent ion implantation. Consequently, the ion implantation profiles for core transistors and I/O transistors are maintained for enhanced performance and reliability for each transistor type.

摘要翻译： 集成电路制造过程在制造I / O设备期间选择性地阻挡硅化物形成，以增强其ESD性能而不影响核心器件的性能。 在示例性实施例中，间隔电介质覆盖MOS结构，使得可以保护栅极免受过程退化。 屏蔽间隔电介质以限定硅化阻挡区和硅化接受区。 在接受硅化物的区域中去除间隔电介质。 硅化阻挡区保护晶体管器件免受后续离子注入。 因此，保持核心晶体管和I / O晶体管的离子注入分布，以提高每个晶体管类型的性能和可靠性。

公开(公告)号：US20130070524A1

公开(公告)日：2013-03-21

申请号：US13239194

申请日：2011-09-21

申请人： Deepanshu Dutta ,  Dana Lee ,  Jeffrey Lutze

发明人： Deepanshu Dutta ,  Dana Lee ,  Jeffrey Lutze

IPC分类号： G11C16/10

CPC分类号： G11C16/04 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3495 ,  G11C2211/5644

摘要： Dynamically determining read levels on chip (e.g., memory die) is disclosed herein. One method comprises reading a group of non-volatile storage elements on a memory die at a first set of read levels. Results of the two most recent of the read levels are stored on the memory die. A count of how many of the non-volatile storage elements in the group showed a different result between the reads for the two most recent read levels is determined. The determining is performed on the memory die using the results stored on the memory die. A dynamic read level is determined for distinguishing between a first pair of adjacent data states of the plurality of data states based on the read level when the count reaches a pre-determined criterion. Note that the read level may be dynamically determined on the memory die.

摘要翻译： 本文公开了动态地确定芯片上的读取电平（例如，存储器管芯）。 一种方法包括以第一组读取级别在存储器管芯上读取一组非易失性存储元件。 两个最新的读取电平的结果存储在存储器管芯上。 确定组中有多少非易失性存储元件在两个最新读取级别的读取之间显示不同的结果。 使用存储在存储器管芯上的结果在存储器管芯上进行确定。 当计数达到预定标准时，基于读取级别来确定动态读取级别以区分多个数据状态的第一对相邻数据状态。 注意，读取电平可以在存储器管芯上动态地确定。

公开(公告)号：US20110170358A1

公开(公告)日：2011-07-14

申请号：US12638853

申请日：2009-12-15

申请人： Changyuan Chen ,  Jeffrey Lutze ,  Yingda Dong ,  Hua-Ling Hsu

发明人： Changyuan Chen ,  Jeffrey Lutze ,  Yingda Dong ,  Hua-Ling Hsu

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G10L15/26 ,  G11C2211/5621

摘要： A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target. Non-volatile storage elements being programmed to a first set of one or more targets are verified to determine whether they have reached their target and are locked out of further programming if it is determined that they have reached their target. Non-volatile storage elements being programmed to the second set of one or more targets are tested to determine the number of fast programming bits. When the number of fast bits for a particular target is greater than a threshold, then programming stops for the non-volatile storage elements being programmed to the particular target.

摘要翻译： 对一组非易失性存储元件进行编程处理以便存储数据。 在编程过程中，执行一个或多个验证操作以确定非易失性存储元件是否已经达到其目标。 对被编程到一个或多个目标的第一组的非易失性存储元件进行验证以确定它们是否已经达到其目标，并且如果确定它们已经达到其目标，则被锁定进一步编程。 被编程到一个或多个目标的第二组的非易失性存储元件被测试以确定快速编程位的数量。 当特定目标的快速位数大于阈值时，则对于被编程到特定目标的非易失性存储元件的编程停止。

公开(公告)号：US07944749B2

公开(公告)日：2011-05-17

申请号：US11614879

申请日：2006-12-21

申请人： Dana Lee ,  Jeffrey Lutze

发明人： Dana Lee ,  Jeffrey Lutze

IPC分类号： G11C16/04

CPC分类号： G11C16/3418

摘要： A low voltage method of programming a selected non-volatile memory cell in a memory array having a gate node coupled to a wordline WL(n) and a drain node connected to a selected bitline by injecting hot carriers from a drain region of an injecting memory cell having a gate node coupled to a next neighbor wordline WL(n−1) into a floating gate of the selected non-volatile memory cell on the wordline WL(n).

摘要翻译： 一种低电压方法，通过从注入存储器的漏极区域注入热载流子来对存储器阵列中的所选择的非易失性存储单元进行编程，所述存储器阵列具有耦合到字线WL（n）的栅极节点和连接到选定位线的漏极节点 小区具有耦合到下一个相邻字线WL（n-1）的门节点到位于字线WL（n）上的所选择的非易失性存储器单元的浮动栅极。

公开(公告)号：US07425744B2

公开(公告)日：2008-09-16

申请号：US11540262

申请日：2006-09-29

申请人： Nima Mokhlesi ,  Jeffrey Lutze

发明人： Nima Mokhlesi ,  Jeffrey Lutze

IPC分类号： H01L27/12

CPC分类号： H01L27/11 ,  H01L21/28273 ,  H01L21/823437 ,  H01L27/1104 ,  H01L27/115 ,  Y10S257/903

摘要： Various embodiments are directed to different methods and systems relating to design and implementation of memory cells such as, for example, static random access memory (SRAM) cells. In one embodiment, a memory cell may include a first layer of conductive material and a second layer of conductive material. The first layer may include a first gate region and a first interconnect region, and the second layer of conductive material may include a second gate region and a second interconnect region. It will be appreciated that the various techniques described herein for using multiple layers of conductive material to form interconnect regions and/or gate regions of memory cells provides extra degrees of freedom in fine tuning memory cell parameters such as, for example, oxide thickness, threshold voltage, maximum allowed gate voltage, etc.

摘要翻译： 各种实施例涉及与诸如静态随机存取存储器（SRAM）单元等存储单元的设计和实现有关的不同方法和系统。 在一个实施例中，存储单元可以包括第一导电材料层和第二导电材料层。 第一层可以包括第一栅极区域和第一互连区域，并且第二层导电材料可以包括第二栅极区域和第二互连区域。 应当理解，本文描述的用于使用多层导电材料形成存储器单元的互连区域和/或栅极区域的各种技术在微调存储器单元参数中提供了额外的自由度，例如，氧化物厚度，阈值 电压，最大允许栅极电压等

公开(公告)号：US20070086247A1

公开(公告)日：2007-04-19

申请号：US11250735

申请日：2005-10-14

申请人： Jeffrey Lutze ,  Yan Li ,  Siu Chan

发明人： Jeffrey Lutze ,  Yan Li ,  Siu Chan

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C16/3427

摘要： The effects of bit line-to-bit line coupling in a non-volatile memory are addressed. An inhibit voltage is applied on a bit line of a storage element to be programmed to inhibit programming during a portion of a program voltage. The inhibit voltage is subsequently removed during the program voltage to allow programming to occur. Due to the proximity of bit lines, the change in the bit line voltage is coupled to a neighboring unselected bit line, reducing the neighboring bit line voltage to a level which might be sufficient to open a select gate and discharge a boost voltage. To prevent this, the select gate voltage is temporarily adjusted during the change in the bit line voltage to ensure that the biasing of the select gate on the unselected bit line is not sufficient to open the select gate.

摘要翻译： 解决位线对位线耦合在非易失性存储器中的影响。 在编程的存储元件的位线上施加禁止电压，以在编程电压的一部分期间禁止编程。 随后在编程电压期间去除抑制电压以允许编程发生。 由于位线的接近，位线电压的变化被耦合到相邻的未选位线，将相邻的位线电压减小到可能足以打开选择栅极并放电升压电压的电平。 为了防止这种情况，在位线电压变化期间临时调整选择栅极电压，以确保未选定位线上的选择栅极的偏置不足以打开选择栅极。

公开(公告)号：US20070076485A1

公开(公告)日：2007-04-05

申请号：US11469727

申请日：2006-09-01

申请人： Jeffrey Lutze ,  Tuan Pham ,  Henry Chien ,  George Matamis

发明人： Jeffrey Lutze ,  Tuan Pham ,  Henry Chien ,  George Matamis

IPC分类号： G11C11/34

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825

摘要： Floating gate structures are disclosed that have a projection that extends away from the surface of a substrate. This projection may provide the floating gate with increased surface area for coupling the floating gate and the control gate. In one embodiment, the word line extends downwards on each side of the floating gate to shield adjacent floating gates in the same string. In another embodiment, a process for fabricating floating gates with projections is disclosed. The projection may be formed so that it is self-aligned to the rest of the floating gate.

摘要翻译： 公开了浮动栅极结构，其具有远离衬底的表面延伸的突起。 该突起可以为浮动栅极提供增加的表面积，用于耦合浮动栅极和控制栅极。 在一个实施例中，字线在浮动栅极的每一侧向下延伸以屏蔽相同串中的相邻浮动栅极。 在另一个实施例中，公开了一种用于制造具有突起的浮动栅极的工艺。 突起可以形成为使得其与浮动栅极的其余部分自对准。

公开(公告)号：US20070025145A1

公开(公告)日：2007-02-01

申请号：US11470932

申请日：2006-09-07

申请人： Nima Mokhlesi ,  Jeffrey Lutze

发明人： Nima Mokhlesi ,  Jeffrey Lutze

IPC分类号： G11C16/04

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/7881

摘要： A non-volatile memory device has a channel region between source/drain regions, a floating gate, a control gate, a first dielectric region between the channel region and the floating gate, and a second dielectric region between the floating gate and the control gate. The first dielectric region includes a high-K material. The non-volatile memory device is programmed and/or erased by transferring charge between the floating gate and the control gate via the second dielectric region.

摘要翻译： 非易失性存储器件在源极/漏极区域之间具有沟道区域，浮置栅极，控制栅极，沟道区域和浮置栅极之间的第一介电区域以及浮置栅极和控制栅极之间的第二介电区域 。 第一电介质区域包括高K材料。 通过经由第二电介质区域在浮动栅极和控制栅极之间传送电荷来对非易失性存储器件进行编程和/或擦除。