公开(公告)号：US20120112279A1

公开(公告)日：2012-05-10

申请号：US12941042

申请日：2010-11-06

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Keith Kwong Hon Wong ,  Ying Zhang

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Keith Kwong Hon Wong ,  Ying Zhang

IPC分类号： H01L29/772 ,  H01L29/45 ,  H01L21/28

CPC分类号： H01L29/41733 ,  H01L21/28518 ,  H01L23/485 ,  H01L29/665 ,  H01L29/66772 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for contacting an FET device is disclosed. The method includes vertically recessing the device isolation, which exposes a sidewall surface on both the source and the drain. Next, silicidation is performed, resulting in a silicide layer covering both the top surface and the sidewall surface of the source and the drain. Next, metallic contacts are applied in such manner that they engage the silicide layer on both its top and on its sidewall surface. A device characterized as being an FET device structure with enlarged contact areas is also disclosed. The device has a vertically recessed isolation, thereby having an exposed sidewall surface on both the source and the drain. A silicide layer is covering both the top surface and the sidewall surface of both the source and the drain. Metallic contacts to the device engage the silicide on its top surface and on its sidewall surface.

摘要翻译： 公开了一种接触FET器件的方法。 该方法包括垂直凹陷器件隔离，其暴露源极和漏极两侧的侧壁表面。 接下来，进行硅化，得到覆盖源极和漏极的顶表面和侧壁表面的硅化物层。 接下来，以这样的方式施加金属触点，使得它们在其顶部和侧壁表面上接合硅化物层。 还公开了一种特征在于具有扩大的接触面积的FET器件结构的器件。 该装置具有垂直凹入的隔离，从而在源极和漏极两者上具有暴露的侧壁表面。 硅化物层覆盖源极和漏极的顶表面和侧壁表面。 与设备的金属接触件在其顶表面和其侧壁表面上接合硅化物。

公开(公告)号：US20120068267A1

公开(公告)日：2012-03-22

申请号：US12886881

申请日：2010-09-21

申请人： Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Katherine L. Saenger

发明人： Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Katherine L. Saenger

IPC分类号： H01L29/786 ,  H01L21/762

CPC分类号： H01L21/84 ,  H01L21/823807

摘要： Strained Si and strained SiGe on insulator devices, methods of manufacture and design structures is provided. The method includes growing an SiGe layer on a silicon on insulator wafer. The method further includes patterning the SiGe layer into PFET and NFET regions such that a strain in the SiGe layer in the PFET and NFET regions is relaxed. The method further includes amorphizing by ion implantation at least a portion of an Si layer directly underneath the SiGe layer. The method further includes performing a thermal anneal to recrystallize the Si layer such that a lattice constant is matched to that of the relaxed SiGe, thereby creating a tensile strain on the NFET region. The method further includes removing the SiGe layer from the NFET region. The method further includes performing a Ge process to convert the Si layer in the PFET region into compressively strained SiGe.

公开(公告)号：US08138543B2

公开(公告)日：2012-03-20

申请号：US12621460

申请日：2009-11-18

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ghavam G. Shahidi

IPC分类号： H01L27/01

CPC分类号： H01L21/845 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1211 ,  H01L29/785

摘要： A circuit structure is disclosed which contains least one each of three different kinds of devices in a silicon layer on insulator (SOI): a planar NFET device, a planar PFET device, and a FinFET device. A trench isolation surrounds the planar NFET device and the planar PFET device penetrating through the SOI and abutting the insulator. Each of the three different kinds of devices contain a high-k gate dielectric layer and a mid-gap gate metal layer, each containing an identical high-k material and an identical mid-gap metal. Each of the three different kinds of devices have an individually optimized threshold value. A method for fabricating a circuit structure is also disclosed, which method involves defining portions in SOI respectively for three different kinds of devices: for a planar NFET device, for a planar PFET device, and for a FinFET device. The method also includes depositing in common a high-k gate dielectric layer and a mid-gap gate metal layer, and using workfunction modifying layers to individually adjust thresholds for the various kinds of devices.

摘要翻译： 公开了一种电路结构，其包含绝缘体上硅层（SOI）中的三种不同类型的器件中的至少一种：平面NFET器件，平面PFET器件和FinFET器件。 沟槽隔离围绕平面NFET器件，并且平面PFET器件穿透SOI并邻接绝缘体。 三种不同类型的器件中的每一种都包含高k栅极电介质层和中间间隙栅极金属层，每个包含相同的高k材料和相同的中间间隙金属。 三种不同类型的设备中的每一种具有单独优化的阈值。 还公开了一种用于制造电路结构的方法，该方法包括为三种不同类型的器件分别定义SOI中的部分：对于平面NFET器件，用于平面PFET器件和FinFET器件。 该方法还包括共同沉积高k栅极电介质层和中间间隙栅极金属层，并且使用功函数修改层来单独调节各种器件的阈值。

公开(公告)号：US20120061759A1

公开(公告)日：2012-03-15

申请号：US12882490

申请日：2010-09-15

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Ghavam Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Ghavam Shahidi

IPC分类号： H01L29/786 ,  H01L21/782

CPC分类号： H01L29/78654 ,  H01L29/66628 ,  H01L29/66772

摘要： A MOSFET device is formed on top of a semiconductor-on-insulator (SOI) substrate having a semiconductor layer with a thickness ranging from 3 nm to 20 nm. A stair-shape raised extension, a raised source region and a raised drain region (S/D) are formed on top of the SOI substrate. The thinner raised extension region abuts at a thin gate sidewall spacer, lowering the extension resistance without significantly increasing the parasitic resistance. A single epitaxial growth forms the thinner raised extension and the thicker raised S/D preferably simultaneously, reducing the fabrication cost as well as the contact resistance between the raised S/D and the extension. A method of forming the aforementioned MOSFET device is also provided.

摘要翻译： 在具有厚度范围为3nm至20nm的半导体层的绝缘体上半导体（SOI）衬底的顶部上形成MOSFET器件。 在SOI衬底的顶部上形成阶梯形凸起的延伸部，凸起的源极区域和凸起的漏极区域（S / D）。 更薄的凸起的延伸区域邻近薄的栅极侧壁间隔物，降低延伸电阻而不显着增加寄生电阻。 单个外延生长优选同时形成更薄的凸起延伸和较高的凸起S / D，从而降低制造成本以及升高的S / D与延伸部之间的接触电阻。 还提供了形成上述MOSFET器件的方法。

公开(公告)号：US20120049284A1

公开(公告)日：2012-03-01

申请号：US12861976

申请日：2010-08-24

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

IPC分类号： H01L27/12 ,  H01L21/336

CPC分类号： H01L27/1211 ,  H01L27/1203

摘要： In one exemplary embodiment, a semiconductor structure includes: a semiconductor-on-insulator substrate with a top semiconductor layer overlying an insulation layer and the insulation layer overlies a bottom substrate layer; at least one first device at least partially overlying and disposed upon a first portion of the top semiconductor layer, where the first portion has a first thickness, a first width and a first depth; and at least one second device at least partially overlying and disposed upon a second portion of the top semiconductor layer, where the second portion has a second thickness, a second width and a second depth, where at least one of the following holds: the first thickness is greater than the second thickness, the first width is greater than the second width and the first depth is greater than the second depth.

摘要翻译： 在一个示例性实施例中，半导体结构包括：绝缘体上半导体衬底，具有覆盖绝缘层的顶部半导体层，绝缘层覆盖在底部衬底层上; 至少一个第一装置至少部分地覆盖并设置在顶部半导体层的第一部分上，其中第一部分具有第一厚度，第一宽度和第一深度; 以及至少一个第二装置，其至少部分地覆盖并设置在顶部半导体层的第二部分上，其中第二部分具有第二厚度，第二宽度和第二深度，其中以下至少一个成立：第一 厚度大于第二厚度，第一宽度大于第二宽度，第一深度大于第二深度。

公开(公告)号：US08124470B1

公开(公告)日：2012-02-28

申请号：US12892950

申请日：2010-09-29

申请人： Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni

发明人： Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni

IPC分类号： H01L21/8238

CPC分类号： H01L21/84 ,  H01L21/76283 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/7847 ,  H01L29/78603

摘要： A method of forming a strained, semiconductor-on-insulator substrate includes forming a second semiconductor layer on a first semiconductor substrate. The second semiconductor is lattice matched to the first semiconductor substrate such that the second semiconductor layer is subjected to a first directional stress. An active device semiconductor layer is formed over the second semiconductor layer such that the active device semiconductor layer is initially in a relaxed state. One or more trench isolation structures are formed through the active device layer and through the second semiconductor layer so as to relax the second semiconductor layer below the active device layer and impart a second directional stress on the active device layer opposite the first directional stress.

摘要翻译： 形成应变绝缘体上半导体衬底的方法包括在第一半导体衬底上形成第二半导体层。 第二半导体与第一半导体衬底晶格匹配，使得第二半导体层经受第一定向应力。 在第二半导体层上形成有源器件半导体层，使得有源器件半导体层初始处于松弛状态。 通过有源器件层和通过第二半导体层形成一个或多个沟槽隔离结构，以便使有源器件层下方的第二半导体层松弛，并在与第一方向应力相反的有源器件层上施加第二方向应力。

公开(公告)号：US20120043623A1

公开(公告)日：2012-02-23

申请号：US12859414

申请日：2010-08-19

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L21/28114 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/7848

摘要： A semiconductor device is provided that includes a gate structure present on a substrate. The gate structure includes a gate conductor with an undercut region in sidewalls of a first portion of the gate conductor, wherein a second portion of the gate conductor is present over the first portion of the gate conductor and includes a protruding portion over the undercut region. A spacer is adjacent to sidewalls of the gate structure, wherein the spacer includes an extending portion filling the undercut region. A raised source region and a raised drain region is present adjacent to the spacers. The raised source region and the raised drain region are separated from the gate conductor by the extending portion of the spacers.

摘要翻译： 提供一种半导体器件，其包括存在于衬底上的栅极结构。 所述栅极结构包括栅极导体，所述栅极导体在所述栅极导体的第一部分的侧壁中具有底切区域，其中所述栅极导体的第二部分存在于所述栅极导体的所述第一部分之上并且包括在所述底切区域上方的突出部分。 间隔件邻近门结构的侧壁，其中间隔件包括填充底切区域的延伸部分。 凸起的源极区域和隆起的漏极区域邻近间隔物存在。 升高的源极区域和隆起的漏极区域通过间隔物的延伸部分与栅极导体分离。

公开(公告)号：US20120025282A1

公开(公告)日：2012-02-02

申请号：US12848494

申请日：2010-08-02

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

IPC分类号： H01L29/94 ,  H01L27/088 ,  H01L21/336 ,  H01L27/105

CPC分类号： H01L27/1203 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/84 ,  H01L29/66628

摘要： In one exemplary embodiment of the invention, a semiconductor structure includes: a substrate; and a plurality of devices at least partially overlying the substrate, where the plurality of devices include a first device coupled to a second device via a first raised source/drain having a first length, where the first device is further coupled to a second raised source/drain having a second length, where the first device comprises a transistor, where the first raised source/drain and the second raised source/drain at least partially overly the substrate, where the second raised source/drain comprises a terminal electrical contact, where the second length is greater than the first length.

公开(公告)号：US08084309B2

公开(公告)日：2011-12-27

申请号：US12542179

申请日：2009-08-17

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ghavam G. Shahidi

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L21/84 ,  H01L21/823814 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

摘要： A method of fabricating an electronic structure is provided that includes forming a first conductivity doped first semiconductor material on the SOI semiconductor layer of a substrate. The SOI semiconductor layer has a thickness of less than 10 nm. The first conductivity in-situ doped first semiconductor material is removed from a first portion of the SOI semiconductor layer, wherein a remaining portion of the first conductivity in-situ doped first semiconductor material is present on a second portion of SOI semiconductor layer. A second conductivity in-situ doped second semiconductor material is formed on the first portion of the SOI semiconductor layer, wherein a mask prohibits the second conductivity in-situ doped semiconductor material from being formed on the second portion of the SOI semiconductor layer. The dopants from the first and second conductivity in-situ doped semiconductor materials are diffused into the first semiconductor layer to form dopant regions.

摘要翻译： 提供一种制造电子结构的方法，其包括在衬底的SOI半导体层上形成第一导电掺杂的第一半导体材料。 SOI半导体层的厚度小于10nm。 第一导电性原位掺杂的第一半导体材料从SOI半导体层的第一部分去除，其中第一导电性原位掺杂的第一半导体材料的剩余部分存在于SOI半导体层的第二部分上。 第二导电性原位掺杂的第二半导体材料形成在SOI半导体层的第一部分上，其中掩模禁止在SOI半导体层的第二部分上形成第二导电性原位掺杂半导体材料。 来自第一和第二导电性原位掺杂半导体材料的掺杂剂扩散到第一半导体层中以形成掺杂区域。

公开(公告)号：US20110309446A1

公开(公告)日：2011-12-22

申请号：US12816399

申请日：2010-06-16

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

IPC分类号： H01L27/12 ,  H01L21/8238 ,  H01L29/786 ,  H01L21/336

CPC分类号： H01L29/66477 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78618

摘要： A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate; forming a spacer layer over the semiconductor substrate and patterned gate structure; removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and forming a raised source/drain (RSD) structure over the semiconductor substrate and adjacent the vertical sidewall spacer, wherein the RSD structure has a substantially vertical sidewall profile so as to abut the vertical sidewall spacer and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the patterned gate structure.

摘要翻译： 一种形成晶体管器件的方法包括在半导体衬底上形成图案化栅极结构; 在半导体衬底上形成间隔层和图案化栅极结构; 去除间隔层的水平设置部分，以形成邻近图案化栅极结构的垂直侧壁间隔物; 以及在所述半导体衬底上并且邻近所述垂直侧壁间隔物形成升高的源极/漏极（RSD）结构，其中所述RSD结构具有基本上垂直的侧壁轮廓，以便邻接所述垂直侧壁间隔物并产生压缩和拉伸应变之一 在图案化的栅极结构下方的半导体衬底的沟道区上。