公开(公告)号：US07445987B2

公开(公告)日：2008-11-04

申请号：US11756927

申请日：2007-06-01

申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Geng Wang

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Geng Wang

IPC分类号： H01L21/8242 ,  H01L21/20

CPC分类号： H01L27/10867 ,  H01L27/1087 ,  H01L29/66181 ,  H01L29/945

摘要： The present invention includes a method for forming a memory array and the memory array produced therefrom. Specifically, the memory array includes at least one first-type memory device, each of the at least one first-type memory device comprising a first transistor and a first underlying capacitor that are in electrical contact to each other through a first buried strap, where the first buried strap positioned on a first collar region; and at least one second-type memory cell, where each of the at least are second-type memory device comprises a second transistor and a second underlying capacitor that are in electrical contact through an offset buried strap, where the offset buried strap is positioned on a second collar region, wherein the second collar region has a length equal to the first collar region.

摘要翻译： 本发明包括一种用于形成存储器阵列的方法和由其制成的存储器阵列。 具体而言，存储器阵列包括至少一个第一型存储器件，至少一个第一型存储器件中的每一个包括通过第一掩埋带彼此电接触的第一晶体管和第一底层电容器，其中 位于第一环区的第一掩埋带; 以及至少一个第二类型存储单元，其中至少第二类型存储器件中的每一个包括第二晶体管和第二底层电容器，所述第二晶体管和第二底层电容器通过偏移掩埋带电接触，其中所述偏移掩埋带位于 第二衣领区域，其中第二衣领区域具有等于第一衣领区域的长度。

公开(公告)号：US20080169494A1

公开(公告)日：2008-07-17

申请号：US12053692

申请日：2008-03-24

申请人： Kangguo Cheng ,  Ramachandra Divakaruni

发明人： Kangguo Cheng ,  Ramachandra Divakaruni

IPC分类号： H01L27/12

CPC分类号： H01L29/7827 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/10841 ,  H01L27/10876 ,  H01L29/66666 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure and method of forming a body contact for a semiconductor-on-insulator trench device. The method including: forming set of mandrels on a top surface of a substrate, each mandrel of the set of mandrels arranged on a different corner of a polygon and extending above the top surface of the substrate, a number of mandrels in the set of mandrels equal to a number of corners of the polygon; forming sidewall spacers on sidewalls of each mandrel of the set of mandrels, sidewalls spacers of each adjacent pair of mandrels merging with each other and forming a unbroken wall defining an opening in an interior region of the polygon, a region of the substrate exposed in the opening; etching a contact trench in the substrate in the opening; and filling the contact trench with an electrically conductive material to form the contact.

摘要翻译： 形成绝缘体上半导体沟槽器件的体接触的结构和方法。 该方法包括：在基板的顶表面上形成一组心轴，该组心轴的每个心轴布置在多边形的不同角上并且在衬底的顶表面上方延伸，该心轴组中的多个心轴 等于多边形的多个角; 在所述一组心轴的每个心轴的侧壁上形成侧壁间隔件，每个相邻的一对心轴的侧壁间隔件彼此合并并且形成在多边形的内部区域中限定开口的不间断的壁， 开口 蚀刻开口中的衬底中的接触沟槽; 以及用导电材料填充接触沟槽以形成接触。

公开(公告)号：US20080135874A1

公开(公告)日：2008-06-12

申请号：US12015272

申请日：2008-01-16

申请人： Kangguo CHENG ,  Ramachandra Divakaruni

发明人： Kangguo CHENG ,  Ramachandra Divakaruni

IPC分类号： H01L29/24 ,  H01L21/20

CPC分类号： H01L29/1054 ,  H01L21/823412 ,  H01L29/739 ,  H01L29/78687

摘要： A method that includes forming a pattern of strained material and relaxed material on a substrate; forming a strained device in the strained material; and forming a non-strained device in the relaxed material is disclosed. In one embodiment, the strained material is silicon (Si) in either a tensile or compressive state, and the relaxed material is Si in a normal state. A buffer layer of silicon germanium (SiGe), silicon carbon (SiC), or similar material is formed on the substrate and has a lattice constant/structure mis-match with the substrate. A relaxed layer of SiGe, SiC, or similar material is formed on the buffer layer and places the strained material in the tensile or compressive state. In another embodiment, carbon-doped silicon or germanium-doped silicon is used to form the strained material. The structure includes a multi-layered substrate having strained and non-strained materials patterned thereon.

摘要翻译： 一种包括在基板上形成应变材料和松弛材料的图案的方法; 在应变材料中形成应变装置; 并且公开了在松弛材料中形成非应变装置。 在一个实施例中，应变材料是处于拉伸或压缩状态的硅（Si），松弛材料是处于正常状态的Si。 在衬底上形成硅锗（SiGe），硅碳（SiC）或类似材料的缓冲层，其晶格常数/结构与衬底失配。 在缓冲层上形成SiGe，SiC或类似材料的松散层，并将应变材料置于拉伸或压缩状态。 在另一个实施例中，使用掺碳硅或锗掺杂硅来形成应变材料。 该结构包括具有图案化的应变和非应变材料的多层基底。

公开(公告)号：US20080102569A1

公开(公告)日：2008-05-01

申请号：US12002828

申请日：2007-12-19

申请人： Kangguo Cheng ,  Gary Bronner ,  Ramachandra Divakaruni ,  Carl Radens

发明人： Kangguo Cheng ,  Gary Bronner ,  Ramachandra Divakaruni ,  Carl Radens

IPC分类号： H01L21/336

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L29/66666 ,  H01L29/78642

摘要： A method of fabricating a vertical field effect transistor (“FET”) is provided which includes a transistor body region and source and drain regions disposed in a single-crystal semiconductor-on-insulator (“SOI”) region of a substrate adjacent a sidewall of a trench. The substrate includes a buried insulator layer underlying the SOI region and a bulk region underlying the buried insulator layer. A buried strap conductively connects the SOI region to a lower node disposed below the SOI region and a body contact extends from the transistor body region to the bulk region of the substrate, the body contact being insulated from the buried strap.

摘要翻译： 提供一种制造垂直场效应晶体管（“FET”）的方法，其包括晶体管本体区域和设置在邻近侧壁的衬底的单晶半导体绝缘体（“SOI”）区域中的源极和漏极区域 的沟渠 衬底包括在SOI区域下面的掩埋绝缘体层和埋在掩埋绝缘体层下面的主体区域。 掩埋带导电地将SOI区域连接到设置在SOI区域下方的下部节点，并且主体接触从晶体管本体区域延伸到衬底的主体区域，身体接触部与掩埋带绝缘。

公开(公告)号：US07348252B2

公开(公告)日：2008-03-25

申请号：US11820713

申请日：2007-06-19

申请人： Kangguo Cheng ,  Ramachandra Divakaruni

发明人： Kangguo Cheng ,  Ramachandra Divakaruni

IPC分类号： H01L21/76 ,  H01L21/30

CPC分类号： H01L29/66772 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/76254 ,  H01L21/76275 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

摘要： A method for forming a bonded SOI wafer is provided in which a first wafer having a single-crystal semiconductor region has a first dielectric layer disposed at an outer surface of the first wafer and a plurality of dielectric filled trenches extending from the outer surface inwardly into the single-crystal semiconductor region. The outer surface of the first wafer can then be bonded to the outer surface of a second wafer having a second single-crystal semiconductor region to form a bonded wafer having a bulk single-crystal semiconductor region, a buried dielectric layer overlying the bulk single-crystal semiconductor region, and a single-crystal semiconductor-on-insulator layer overlying the buried dielectric layer. The dielectric filled trenches may extend upwardly from the buried dielectric layer into the single-crystal semiconductor-on-insulator layer. The thickness of the semiconductor-on-insulator layer may then be reduced until uppermost surfaces of at least some of the dielectric filled trenches are at least partially exposed.

摘要翻译： 提供了一种用于形成接合的SOI晶片的方法，其中具有单晶半导体区域的第一晶片具有设置在第一晶片的外表面的第一电介质层和从外表面向内延伸的多个电介质填充的沟槽 单晶半导体区域。 然后可以将第一晶片的外表面接合到具有第二单晶半导体区域的第二晶片的外表面，以形成具有大块单晶半导体区域的接合晶片，覆盖大块单晶半导体区域的掩埋电介质层， 晶体半导体区域和覆盖在掩埋介电层上的绝缘体上单层半导体层。 电介质填充的沟槽可以从掩埋的介电层向上延伸到绝缘体上的单晶半导体层中。 然后可以减小绝缘体上半导体层的厚度，直到至少一些电介质填充沟槽的最上表面至少部分露出。

公开(公告)号：US20080061317A1

公开(公告)日：2008-03-13

申请号：US11931836

申请日：2007-10-31

申请人： Kangguo Cheng ,  Ramachandra Divakaruni

发明人： Kangguo Cheng ,  Ramachandra Divakaruni

IPC分类号： H01L29/267 ,  H01L21/20

CPC分类号： H01L29/1054 ,  H01L21/823412 ,  H01L29/739 ,  H01L29/78687

摘要： A method that includes forming a pattern of strained material and relaxed material on a substrate; forming a strained device in the strained material; and forming a non-strained device in the relaxed material is disclosed. In one embodiment, the strained material is silicon (Si) in either a tensile or compressive state, and the relaxed material is Si in a normal state. A buffer layer of silicon germanium (SiGe), silicon carbon (SiC), or similar material is formed on the substrate and has a lattice constant/structure mis-match with the substrate. A relaxed layer of SiGe, SiC, or similar material is formed on the buffer layer and places the strained material in the tensile or compressive state. In another embodiment, carbon-doped silicon or germanium-doped silicon is used to form the strained material. The structure includes a multi-layered substrate having strained and non-strained materials patterned thereon.

公开(公告)号：US20070284612A1

公开(公告)日：2007-12-13

申请号：US11423280

申请日：2006-06-09

申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl John Radens

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl John Radens

IPC分类号： H01L31/00

CPC分类号： H01L29/66181 ,  H01L27/10867

摘要： Structures and methods for forming the same. A semiconductor fabrication method comprises a step of providing a semiconductor structure. The semiconductor structure includes a semiconductor substrate and a capacitor electrode on the semiconductor substrate. The capacitor electrode comprises dopants, and is electrically insulated from the semiconductor substrate by a capacitor dielectric layer. The semiconductor structure further includes a semiconductor layer on the semiconductor substrate. The semiconductor layer comprises a trench which partially but not completely overlaps the capacitor electrode. The method further comprises the step of causing some of the dopants of the capacitor electrode to diffuse into the semiconductor layer, resulting in a doped source/drain region. The doped source/drain region overlaps the capacitor electrode and abuts a sidewall of the trench.

摘要翻译： 用于形成它的结构和方法。 半导体制造方法包括提供半导体结构的步骤。 半导体结构包括在半导体衬底上的半导体衬底和电容器电极。 电容器电极包括掺杂剂，并且通过电容器介电层与半导体衬底电绝缘。 半导体结构还包括半导体衬底上的半导体层。 半导体层包括与电容器电极部分但不完全重叠的沟槽。 该方法还包括使电容器电极的一些掺杂剂扩散到半导体层中的步骤，产生掺杂的源极/漏极区域。 掺杂源极/漏极区域与电容器电极重叠并邻接沟槽的侧壁。

公开(公告)号：US20070224757A1

公开(公告)日：2007-09-27

申请号：US11756927

申请日：2007-06-01

申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Geng Wang

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Geng Wang

IPC分类号： H01L21/8242

CPC分类号： H01L27/10867 ,  H01L27/1087 ,  H01L29/66181 ,  H01L29/945

摘要： The present invention includes a method for forming a memory array and the memory array produced therefrom. Specifically, the memory array includes at least one first-type memory device, each of the at least one first-type memory device comprising a first transistor and a first underlying capacitor that are in electrical contact to each other through a first buried strap, where the first buried strap positioned on a first collar region; and at least one second-type memory cell, where each of the at least are second-type memory device comprises a second transistor and a second underlying capacitor that are in electrical contact through an offset buried strap, where the offset buried strap is positioned on a second collar region, wherein the second collar region has a length equal to the first collar region.

摘要翻译： 本发明包括一种用于形成存储器阵列的方法和由其制成的存储器阵列。 具体而言，存储器阵列包括至少一个第一型存储器件，至少一个第一型存储器件中的每一个包括通过第一掩埋带彼此电接触的第一晶体管和第一底层电容器，其中 位于第一环区的第一掩埋带; 以及至少一个第二类型存储单元，其中至少第二类型存储器件中的每一个包括第二晶体管和第二底层电容器，所述第二晶体管和第二底层电容器通过偏移掩埋带电接触，其中所述偏移掩埋带位于 第二衣领区域，其中第二衣领区域具有等于第一衣领区域的长度。

公开(公告)号：US07247536B2

公开(公告)日：2007-07-24

申请号：US11085663

申请日：2005-03-21

申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Chun-Yung Sung

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Chun-Yung Sung

IPC分类号： H01L21/8242

CPC分类号： H01L27/10876 ,  H01L27/0207 ,  H01L27/10864 ,  H01L27/1087 ,  H01L29/945

摘要： A method and structure for a memory storage cell in a semiconductor substrate includes forming a dopant source material over a lower portion of a deep trench formed in the substrate. An upper portion of the trench is shaped to a generally rectangular configuration, and the dopant source material is annealed so as to form a buried plate of a trench capacitor. The buried plate is self aligned to the shaped upper portion of the trench.

摘要翻译： 半导体衬底中的存储单元的方法和结构包括在衬底中形成的深沟槽的下部形成掺杂剂源材料。 沟槽的上部被成形为大致矩形的构造，并且掺杂剂源材料被退火以形成沟槽电容器的掩埋板。 掩埋板与沟槽的成形上部自对准。

公开(公告)号：US20070164397A1

公开(公告)日：2007-07-19

申请号：US11715751

申请日：2007-03-08

申请人： Kangguo Cheng ,  Ramachandra Divakaruni

发明人： Kangguo Cheng ,  Ramachandra Divakaruni

IPC分类号： H01L29/00

CPC分类号： H01L27/1087 ,  H01L29/945

摘要： A method is provided for making a buried plate region in a semiconductor substrate. According to such method, a trench is a single-crystal semiconductor region of a substrate is etched to form a trench elongated in a direction extending downwardly from a major surface of the substrate. A dopant source layer is formed to overlie a lower portion of the trench sidewall but not an upper portion of the trench sidewall. A layer consisting essentially of semiconductor material is epitaxially grown onto a single-crystal semiconductor region exposed at the upper portion of the trench sidewall above the dopant source layer. Through annealing, a dopant is then driven from the dopant source layer into the single-crystal semiconductor material of the substrate adjacent to the lower portion to form a buried plate. Then, the dopant source layer is removed and an isolation collar is formed along at least a part of the upper portion.

摘要翻译： 提供了一种在半导体衬底中制造掩埋板区域的方法。 根据这种方法，沟槽是衬底的单晶半导体区域被蚀刻以形成在从衬底的主表面向下延伸的方向上延伸的沟槽。 掺杂剂源层形成为覆盖在沟槽侧壁的下部，而不是沟槽侧壁的上部。 基本上由半导体材料组成的层被外延生长到暴露在掺杂剂源层上方的沟槽侧壁上部的单晶半导体区域上。 通过退火，然后将掺杂剂从掺杂剂源层驱动到与下部相邻的衬底的单晶半导体材料中以形成掩埋板。 然后，去除掺杂剂源层，沿着上部的至少一部分形成隔离环。