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公开(公告)号：US07615816B2
公开(公告)日：2009-11-10
申请号：US11692473
申请日：2007-03-28
IPC分类号： H01L27/108
CPC分类号： H01L27/10876 , H01L27/0207 , H01L27/10864 , H01L27/1087 , H01L29/945
摘要： A buried plate region for a semiconductor memory storage capacitor is self aligned with respect to an upper portion of a deep trench containing the memory storage capacitor.
摘要翻译： 用于半导体存储器存储电容器的掩埋板区域相对于包含存储器存储电容器的深沟槽的上部自对准。
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公开(公告)号：US07247536B2
公开(公告)日：2007-07-24
申请号：US11085663
申请日：2005-03-21
IPC分类号： H01L21/8242
CPC分类号： H01L27/10876 , H01L27/0207 , H01L27/10864 , H01L27/1087 , H01L29/945
摘要： A method and structure for a memory storage cell in a semiconductor substrate includes forming a dopant source material over a lower portion of a deep trench formed in the substrate. An upper portion of the trench is shaped to a generally rectangular configuration, and the dopant source material is annealed so as to form a buried plate of a trench capacitor. The buried plate is self aligned to the shaped upper portion of the trench.
摘要翻译： 半导体衬底中的存储单元的方法和结构包括在衬底中形成的深沟槽的下部形成掺杂剂源材料。 沟槽的上部被成形为大致矩形的构造，并且掺杂剂源材料被退火以形成沟槽电容器的掩埋板。 掩埋板与沟槽的成形上部自对准。
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公开(公告)号：US07122437B2
公开(公告)日：2006-10-17
申请号：US10741203
申请日：2003-12-19
申请人： Thomas W. Dyer , Chun-yung Sung , Ravikumar Ramachandran , Ramachandra Divakaruni , Carl Radens
发明人： Thomas W. Dyer , Chun-yung Sung , Ravikumar Ramachandran , Ramachandra Divakaruni , Carl Radens
IPC分类号： H01L21/8242
CPC分类号： H01L27/1087 , H01L29/945
摘要： A deep trench capacitor used in a trench DRAM includes a buried plate and an isolation collar. The deep trench is bottle-shaped, and the isolation collar is formed in upper portion of the wider region of the bottle-shaped trench. The buried plate surrounds the lower portion of the wider part of the bottle-shaped trench, and hemispherical grain polysilicon lines the walls of at least the lower portion of the wider part of the trench. A nitride liner layer lines the inner walls of the oxide collar and prevents diffusion of dopant through the oxide collar into the substrate when the HSG polysilicon and the doped buried plate are formed. The buried plate region is self-aligned to the isolation collar. The depth of the top of the wider part of the bottle shape and the bottom depth of the isolation collar are determined by successive resist deposition and recessing steps.
摘要翻译： 在沟槽DRAM中使用的深沟槽电容器包括掩埋板和隔离环。 深沟是瓶形的，并且隔离套环形成在瓶形沟槽的较宽区域的上部。 掩埋板围绕瓶形沟槽的较宽部分的下部，半球状晶粒多晶硅线路至少沟槽较宽部分的下部的壁。 当形成HSG多晶硅和掺杂掩埋板时，氮化物衬垫层线化氧化物环的内壁并防止掺杂剂通过氧化物环到衬底中的扩散。 掩埋板区域与隔离套环自对准。 通过连续的抗蚀剂沉积和凹陷步骤确定瓶子形状的较宽部分的顶部的深度和隔离环的底部深度。
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公开(公告)号：US06933192B1
公开(公告)日：2005-08-23
申请号：US10709472
申请日：2004-05-07
IPC分类号： H01L21/334 , H01L21/8242 , H01L29/94
CPC分类号： H01L27/1087 , H01L29/66181 , H01L29/945
摘要： A method of forming a buried dielectric collar around a trench and of forming a trench capacitor, the buried dielectric collar formed by: (a) forming the trench in a substrate; (b) forming a multilayer coating on sidewalls and a bottom of the trench; (c) removing a continuous band of the multilayer coating from the sidewalls a fixed distance from a top of the trench to expose a continuous band substrate in the sidewalls of the trench; (d) etching, in said exposed band of substrate, a lateral trench extending into said substrate in said sidewalls of said trench; and (e) filling the lateral trench with a dielectric material to form the buried dielectric collar. The trench capacitor is formed by filling the trench or its variants with polysilicon.
摘要翻译： 一种在沟槽周围形成埋置的介电环圈并形成沟槽电容器的方法，所述埋入介质套管由以下部分形成：（a）在衬底中形成沟槽; （b）在沟槽的侧壁和底部上形成多层涂层; （c）从沟槽的顶部固定的距离从侧壁去除多层涂层的连续带，以暴露在沟槽的侧壁中的连续带状衬底; （d）在所述衬底的所述暴露带中蚀刻在所述沟槽的所述侧壁中延伸到所述衬底中的横向沟槽; 和（e）用电介质材料填充横向沟槽以形成埋入的电介质套环。 通过用多晶硅填充沟槽或其变体形成沟槽电容器。
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公开(公告)号：US20050133846A1
公开(公告)日：2005-06-23
申请号：US10741203
申请日：2003-12-19
IPC分类号： H01L21/8242 , H01L29/94 , H01L27/108 , H01L31/119
CPC分类号： H01L27/1087 , H01L29/945
摘要： A deep trench capacitor used in a trench DRAM includes a buried plate and an isolation collar. The deep trench is bottle-shaped, and the isolation collar is formed in upper portion of the wider region of the bottle-shaped trench. The buried plate surrounds the lower portion of the wider part of the bottle-shaped trench, and hemispherical grain polysilicon lines the walls of at least the lower portion of the wider part of the trench. A nitride liner layer lines the inner walls of the oxide collar and prevents diffusion of dopant through the oxide collar into the substrate when the HSG polysilicon and the doped buried plate are formed. The buried plate region is self-aligned to the isolation collar. The depth of the top of the wider part of the bottle shape and the bottom depth of the isolation collar are determined by successive resist deposition and recessing steps.
摘要翻译： 在沟槽DRAM中使用的深沟槽电容器包括掩埋板和隔离环。 深沟是瓶形的，并且隔离套环形成在瓶形沟槽的较宽区域的上部。 掩埋板围绕瓶形沟槽的较宽部分的下部，半球状晶粒多晶硅线路至少沟槽较宽部分的下部的壁。 当形成HSG多晶硅和掺杂掩埋板时，氮化物衬垫层线化氧化物环的内壁并防止掺杂剂通过氧化物环到衬底中的扩散。 掩埋板区域与隔离套环自对准。 通过连续的抗蚀剂沉积和凹陷步骤确定瓶子形状的较宽部分的顶部的深度和隔离环的底部深度。
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6.发明申请METHOD AND STRUCTURE FOR FORMING CAPACITORS AND MEMORY DEVICES ON SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATES 有权在半导体绝缘体（SOI）衬底上形成电容器和存储器件的方法和结构公开(公告)号：US20110169065A1
公开(公告)日：2011-07-14
申请号：US12686403
申请日：2010-01-13
IPC分类号： H01L27/06 , H01L21/8242
CPC分类号： H01L21/84 , H01L27/0207 , H01L27/1087 , H01L27/10894 , H01L27/1203 , H01L29/66181
摘要： A device is provided that includes memory, logic and capacitor structures on a semiconductor-on-insulator (SOI) substrate. In one embodiment, the device includes a semiconductor-on-insulator (SOI) substrate having a memory region and a logic region. Trench capacitors are present in the memory region and the logic region, wherein each of the trench capacitors is structurally identical. A first transistor is present in the memory region in electrical communication with a first electrode of at least one trench capacitor that is present in the memory region. A second transistor is present in the logic region that is physically separated from the trench capacitors by insulating material. In some embodiments, the trench capacitors that are present in the logic region include decoupling capacitors and inactive capacitors. A method for forming the aforementioned device is also provided.
摘要翻译： 提供了一种在绝缘体上半导体（SOI）衬底上包括存储器，逻辑和电容器结构的器件。 在一个实施例中，该器件包括具有存储区域和逻辑区域的绝缘体上半导体（SOI）衬底。 沟槽电容器存在于存储器区域和逻辑区域中，其中每个沟槽电容器在结构上相同。 第一晶体管存在于与存在于存储器区域中的至少一个沟槽电容器的第一电极电连通的存储区域中。 第二晶体管存在于通过绝缘材料与沟槽电容器物理分离的逻辑区域中。 在一些实施例中，存在于逻辑区域中的沟槽电容器包括去耦电容器和无效电容器。 还提供了一种用于形成上述装置的方法。
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7.发明授权Self-aligned body contact for a semiconductor-on-insulator trench device and method of fabricating same 有权绝缘体上半导体沟槽器件的自对准体接触及其制造方法公开(公告)号：US07935998B2
公开(公告)日：2011-05-03
申请号：US12053692
申请日：2008-03-24
IPC分类号： H01L23/02
CPC分类号： H01L29/7827 , H01L21/84 , H01L27/0207 , H01L27/10841 , H01L27/10876 , H01L29/66666 , H01L2924/0002 , H01L2924/00
摘要： A structure and method of forming a body contact for a semiconductor-on-insulator trench device. The method including: forming set of mandrels on a top surface of a substrate, each mandrel of the set of mandrels arranged on a different corner of a polygon and extending above the top surface of the substrate, a number of mandrels in the set of mandrels equal to a number of corners of the polygon; forming sidewall spacers on sidewalls of each mandrel of the set of mandrels, sidewalls spacers of each adjacent pair of mandrels merging with each other and forming a unbroken wall defining an opening in an interior region of the polygon, a region of the substrate exposed in the opening; etching a contact trench in the substrate in the opening; and filling the contact trench with an electrically conductive material to form the contact.
摘要翻译： 形成绝缘体上半导体沟槽器件的体接触的结构和方法。 该方法包括：在基板的顶表面上形成一组心轴，该组心轴的每个心轴布置在多边形的不同角上并且在衬底的顶表面上方延伸，该心轴组中的多个心轴 等于多边形的多个角; 在所述一组心轴的每个心轴的侧壁上形成侧壁间隔件，每个相邻的一对心轴的侧壁间隔件彼此合并并且形成在多边形的内部区域中限定开口的不间断的壁， 开口 蚀刻开口中的衬底中的接触沟槽; 以及用导电材料填充接触沟槽以形成接触。
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公开(公告)号：US07776706B2
公开(公告)日：2010-08-17
申请号：US12169727
申请日：2008-07-09
IPC分类号： H01L21/8234
CPC分类号： H01L27/10867 , H01L27/0207
摘要： A method of forming a trench memory cell includes forming a trench capacitor within a substrate material, the trench capacitor including a node dielectric layer formed within a trench and a conductive capacitor electrode material formed within the trench in contact with the node dielectric layer; forming a strap mask so as cover one side of the trench and removing one or more materials from an uncovered opposite side of the trench; and forming a conductive buried strap material within the trench; wherein the strap mask is patterned in a manner such that a single-sided buried strap is defined within the trench, the single-sided buried strap configured in a manner such that the deep trench capacitor is electrically accessible at only one side of the trench.
摘要翻译： 形成沟槽存储单元的方法包括在衬底材料内形成沟槽电容器，所述沟槽电容器包括形成在沟槽内的节点电介质层和形成在所述沟槽内与所述节点电介质层接触的导电电容器电极材料; 形成带状掩模，以覆盖沟槽的一侧，并从沟槽的未覆盖的相对侧移除一种或多种材料; 以及在所述沟槽内形成导电掩埋带材料; 其中所述带掩模被图案化，使得在所述沟槽内限定单面掩埋带，所述单侧埋入带以使得所述深沟槽电容器仅在所述沟槽的一侧电可访问的方式构造。
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公开(公告)号：US07759188B2
公开(公告)日：2010-07-20
申请号：US12002828
申请日：2007-12-19
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/66666 , H01L29/78642
摘要： A method of fabricating a vertical field effect transistor (“FET”) is provided which includes a transistor body region and source and drain regions disposed in a single-crystal semiconductor-on-insulator (“SOI”) region of a substrate adjacent a sidewall of a trench. The substrate includes a buried insulator layer underlying the SOI region and a bulk region underlying the buried insulator layer. A buried strap conductively connects the SOI region to a lower node disposed below the SOI region and a body contact extends from the transistor body region to the bulk region of the substrate, the body contact being insulated from the buried strap.
摘要翻译： 提供一种制造垂直场效应晶体管（“FET”）的方法，其包括晶体管本体区域和设置在邻近侧壁的衬底的单晶半导体绝缘体（“SOI”）区域中的源极和漏极区域 的沟渠 衬底包括在SOI区域下面的掩埋绝缘体层和埋在掩埋绝缘体层下面的主体区域。 掩埋带导电地将SOI区域连接到设置在SOI区域下方的下部节点，并且主体接触从晶体管本体区域延伸到衬底的主体区域，身体接触部与掩埋带绝缘。
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10.发明授权Self-aligned strap for embedded trench memory on hybrid orientation substrate 失效用于混合取向基板上嵌入式沟槽存储器的自对准带公开(公告)号：US07737482B2
公开(公告)日：2010-06-15
申请号：US11538982
申请日：2006-10-05
IPC分类号： H01L29/76
CPC分类号： H01L27/1203 , H01L21/743 , H01L21/84 , H01L27/10829 , H01L27/10867 , H01L27/1087 , H01L27/1207 , H01L29/78
摘要： Structures including a self-aligned strap for embedded trench memory (e.g., trench capacitor) on hybrid orientation technology (HOT) substrate, and related method, are disclosed. One structure includes a hybrid orientation substrate including a semiconductor-on-insulator (SOI) section and a bulk semiconductor section; a transistor over the SOI section; a trench capacitor in the bulk semiconductor section; and a self-aligned strap extending from a source/drain region of the transistor to an electrode of the trench capacitor. The method does not require additional masks to generate the strap, results in a self-aligned strap and improved device performance. In one embodiment, the strap is a silicide strap.
摘要翻译： 公开了包括用于混合取向技术（HOT）衬底上的嵌入式沟槽存储器（例如，沟槽电容器）的自对准带的结构以及相关方法。 一种结构包括：包含绝缘体上半导体（SOI）部分和体半导体部分的混合取向衬底; SOI部分上的晶体管; 体半导体部分中的沟槽电容器; 以及从晶体管的源极/漏极区域延伸到沟槽电容器的电极的自对准带。 该方法不需要额外的掩模来生成带，导致自对准带和改进的设备性能。 在一个实施例中，带是硅化物带。
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