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    VERTICAL BODY-CONTACTED SOI TRANSISTOR
    1.
    发明申请
    VERTICAL BODY-CONTACTED SOI TRANSISTOR 有权
    垂直接触式SOI晶体管

    公开(公告)号：US20060175660A1

    公开(公告)日：2006-08-10

    申请号：US10906238

    申请日：2005-02-10

    申请人： Kangguo Cheng ,  Gary Bronner ,  Ramachandra Divakaruni ,  Carl Radens

    发明人： Kangguo Cheng ,  Gary Bronner ,  Ramachandra Divakaruni ,  Carl Radens

    IPC分类号： H01L27/12

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L29/66666 ,  H01L29/78642

    摘要： A vertical field effect transistor (“FET”) is provided which includes a transistor body region and source and drain regions disposed in a single-crystal semiconductor-on-insulator (“SOI”) region of a substrate adjacent a sidewall of a trench. The substrate includes a buried insulator layer underlying the SOI region and a bulk region underlying the buried insulator layer. A buried strap conductively connects the SOI region to a lower node disposed below the SOI region and a body contact extends from the transistor body region to the bulk region of the substrate, the body contact being insulated from the buried strap.

    摘要翻译： 提供了垂直场效应晶体管（“FET”），其包括晶体管本体区域和设置在与沟槽的侧壁相邻的衬底的绝缘体上的单晶半导体（“SOI”）区域中的源极和漏极区域。 衬底包括在SOI区域下面的掩埋绝缘体层和埋在掩埋绝缘体层下面的主体区域。 掩埋带导电地将SOI区域连接到设置在SOI区域下方的下部节点，并且主体接触从晶体管本体区域延伸到衬底的主体区域，身体接触部与掩埋带绝缘。

    Method of fabricating vertical body-contacted SOI transistor
    2.
    发明申请
    Method of fabricating vertical body-contacted SOI transistor 失效
    垂直体接触SOI晶体管的制造方法

    公开(公告)号：US20080102569A1

    公开(公告)日：2008-05-01

    申请号：US12002828

    申请日：2007-12-19

    申请人： Kangguo Cheng ,  Gary Bronner ,  Ramachandra Divakaruni ,  Carl Radens

    发明人： Kangguo Cheng ,  Gary Bronner ,  Ramachandra Divakaruni ,  Carl Radens

    IPC分类号： H01L21/336

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L29/66666 ,  H01L29/78642

    摘要： A method of fabricating a vertical field effect transistor (“FET”) is provided which includes a transistor body region and source and drain regions disposed in a single-crystal semiconductor-on-insulator (“SOI”) region of a substrate adjacent a sidewall of a trench. The substrate includes a buried insulator layer underlying the SOI region and a bulk region underlying the buried insulator layer. A buried strap conductively connects the SOI region to a lower node disposed below the SOI region and a body contact extends from the transistor body region to the bulk region of the substrate, the body contact being insulated from the buried strap.

    摘要翻译： 提供一种制造垂直场效应晶体管（“FET”）的方法，其包括晶体管本体区域和设置在邻近侧壁的衬底的单晶半导体绝缘体（“SOI”）区域中的源极和漏极区域 的沟渠 衬底包括在SOI区域下面的掩埋绝缘体层和埋在掩埋绝缘体层下面的主体区域。 掩埋带导电地将SOI区域连接到设置在SOI区域下方的下部节点，并且主体接触从晶体管本体区域延伸到衬底的主体区域，身体接触部与掩埋带绝缘。

    OUT OF THE BOX VERTICAL TRANSISTOR FOR eDRAM ON SOI
    3.
    发明申请
    OUT OF THE BOX VERTICAL TRANSISTOR FOR eDRAM ON SOI 有权
    在SOI上用于eDRAM的盒式垂直晶体管

    公开(公告)号：US20050247966A1

    公开(公告)日：2005-11-10

    申请号：US10709450

    申请日：2004-05-06

    申请人： James Adkisson ,  Gary Bronner ,  Dureseti Chidambarrao ,  Ramachandra Divakaruni ,  Carl Radens

    发明人： James Adkisson ,  Gary Bronner ,  Dureseti Chidambarrao ,  Ramachandra Divakaruni ,  Carl Radens

    IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L31/119

    CPC分类号： H01L27/10841 ,  H01L27/10864 ,  H01L27/10867

    摘要： The present invention provides a vertical memory device formed in a silicon-on-insulator substrate, where a bitline contacting the upper surface of the silicon-on-insulator substrate is electrically connected to the vertical memory device through an upper strap diffusion region formed through a buried oxide layer. The upper strap diffusion region is formed by laterally etching a portion of the buried oxide region to produce a divot, in which doped polysilicon is deposited. The upper strap region diffusion region also provides the source for the vertical transistor of the vertical memory device. The vertical memory device may also be integrated with a support region having logic devices formed atop the silicon-on-insulator substrate.

    摘要翻译： 本发明提供了一种形成在绝缘体上硅衬底上的垂直存储器件，其中接触绝缘体上硅衬底的上表面的位线通过上带扩散区域电连接到垂直存储器件 掩埋氧化层。 上带扩散区域通过横向蚀刻掩埋氧化物区域的一部分而形成，其中沉积掺杂多晶硅。 上带区域扩散区域还为垂直存储器件的垂直晶体管提供源极。 垂直存储器件还可以与具有形成在绝缘体上硅衬底上的逻辑器件的支撑区域集成。

    DRAM cell with buried collar and self-aligned buried strap
    5.
    发明申请
    DRAM cell with buried collar and self-aligned buried strap 失效
    DRAM电池带有埋入式和自对准埋地带

    公开(公告)号：US20050093044A1

    公开(公告)日：2005-05-05

    申请号：US10696151

    申请日：2003-10-29

    申请人： Kangguo Cheng ,  Ramachandra Divkaruni ,  Gary Bronner ,  Carl Radens ,  Oleg Gluschenkov

    发明人： Kangguo Cheng ,  Ramachandra Divkaruni ,  Gary Bronner ,  Carl Radens ,  Oleg Gluschenkov

    IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L31/119

    CPC分类号： H01L27/1087 ,  H01L27/10864 ,  H01L27/10867

    摘要： In a DRAM cell having a trench, a cell capacitor and a cell transistor, a node conducting element connects the cell capacitor to the cell transistor and a collar is disposed about the node conducting element. The collar is disposed in the substrate at least partially, up to entirely outside of the trench. Because the collar is disposed in the substrate outside of the trench, it does not restrict the size of the trench opening. This enables sub-100 nm trenches, using techniques which are compatible with contemporary DRAM process steps. A strap is embedded into a top surface of the collar.

    摘要翻译： 在具有沟槽的DRAM单元，单元电容器和单元晶体管中，节点导电元件将单元电容器连接到单元晶体管，并且环绕节点导电元件设置套环。 轴环至少部分地设置在衬底中，直到完全在沟槽的外部。 因为套环设置在沟槽外部的衬底中，所以不限制沟槽开口的尺寸。 这使得能够使用与当前DRAM工艺步骤兼容的技术的100nm以下的沟槽。 带子被嵌入到衣领的顶表面中。

    Raised sti process for multiple gate ox and sidewall protection on strained Si/SGOI structure with elevated source/drain
    6.
    发明申请
    Raised sti process for multiple gate ox and sidewall protection on strained Si/SGOI structure with elevated source/drain 有权
    用于提高源/漏极的应变Si / SGOI结构的多栅极和侧壁保护的提升过程

    公开(公告)号：US20060128111A1

    公开(公告)日：2006-06-15

    申请号：US11351801

    申请日：2006-02-10

    申请人： Jochen Beintner ,  Gary Bronner ,  Ramachandra Divakaruni ,  Byeong Kim

    发明人： Jochen Beintner ,  Gary Bronner ,  Ramachandra Divakaruni ,  Byeong Kim

    IPC分类号： H01L21/76

    CPC分类号： H01L29/66628 ,  H01L21/76243 ,  H01L21/76251 ,  H01L29/1054 ,  H01L29/41783 ,  H01L29/516 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66742 ,  H01L29/7842 ,  H01L29/78687 ,  Y10S438/938

    摘要： The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack comprising at least a gate dielectric and a gate polySi located on another portion of the strained Si layer; and a raised trench oxide region surrounding the active device region. The present invention also provides a method of forming such a structure. In the inventive method, the gate dielectric is formed prior to trench isolation formation thereby avoiding many of the problems associated with prior art processes in which the trench oxide is formed prior to gate dielectric formation.

    摘要翻译： 本发明提供了一种应变/ SGOI结构，其包括弛豫SiGe层的有源器件区，位于松弛SiGe层顶部的应变Si层，位于应变Si层的一部分顶部的凸起的源/漏区，以及 包括位于应变Si层的另一部分上的至少栅极电介质和栅极多晶硅的堆叠; 以及围绕有源器件区域的凸起的沟槽氧化物区域。 本发明还提供了一种形成这种结构的方法。 在本发明的方法中，在沟槽隔离形成之前形成栅极电介质，从而避免了与在栅极电介质形成之前形成沟槽氧化物的现有技术工艺相关的许多问题。

    Modified gate processing for optimized definition of array and logic devices on same chip
    7.
    发明授权
    Modified gate processing for optimized definition of array and logic devices on same chip 失效
    改进的门处理，用于在同一芯片上优化阵列和逻辑器件的定义

    公开(公告)号：US06548357B2

    公开(公告)日：2003-04-15

    申请号：US10117869

    申请日：2002-04-08

    申请人： Mary E. Weybright ,  Gary Bronner ,  Richard A. Conti ,  Ramachandra Divakaruni ,  Jeffrey Peter Gambino ,  Peter Hoh ,  Uwe Schroeder

    发明人： Mary E. Weybright ,  Gary Bronner ,  Richard A. Conti ,  Ramachandra Divakaruni ,  Jeffrey Peter Gambino ,  Peter Hoh ,  Uwe Schroeder

    IPC分类号： H01L21336

    CPC分类号： H01L27/10894 ,  H01L21/76897 ,  H01L21/823456 ,  H01L27/1052 ,  H01L27/10873

    摘要： Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.

    摘要翻译： 在阵列和支撑器件区域中使用两个不同的栅极导体电介质盖，使得可以在阵列区域中制造位线接触，但是可以使用较薄的硬掩模用于支撑装置区域中的更好的线宽控制。 在支撑掩模蚀刻期间，将较薄的介质盖制成阵列器件区域中的电介质间隔物。 这些介质间隔物允许使阵列栅极导体抗蚀剂线小于最终的栅极导体线宽。 这扩大了阵列栅极导体处理窗口。 第二电介质盖层改善了支撑装置和阵列装置的线宽控制。 在本发明中执行两个单独的栅极导体光刻步骤和栅极导体介电蚀刻，以优化阵列和支撑装置区域中的栅极导体线宽控制。 阵列和支撑装置区域中的栅极导体被同时蚀刻以降低生产成本。 在本发明的另外的实施例中，可以用包括无边界触点的阵列来制造具有或不具有自对准硅的双功能功能支撑器件晶体管。

    DRAM strap: hydrogen annealing for improved strap resistance in high density trench DRAMS
    8.
    发明授权
    DRAM strap: hydrogen annealing for improved strap resistance in high density trench DRAMS 失效
    DRAM带：用于改善高密度沟槽DRAMS中的带状电阻的氢退火

    公开(公告)号：US06495876B1

    公开(公告)日：2002-12-17

    申请号：US09609288

    申请日：2000-06-30

    申请人： Gary Bronner ,  Ramachandra Divakaruni ,  Yoichi Takegawa

    发明人： Gary Bronner ,  Ramachandra Divakaruni ,  Yoichi Takegawa

    IPC分类号： H01L27108

    CPC分类号： H01L21/3003 ,  H01L27/10867

    摘要： A method and structure for a DRAM device which includes a trench within an insulator, a conductor within the trench, a transistor adjacent a first side of the trench, and a shallow trench isolation region formed within a top portion of the conductor on a second side of the trench, opposite the first side, wherein the top portion of the conductor has a curved shape at an edge of the shallow trench isolation region. The curved shape comprises a conductive strap and electrically connects the conductor and the single crystal where the transistor is formed, further comprising a collar oxide surrounding the top portion of the conductor, the collar oxide controlling a shape and location of the curved shape. The curved shape is formed by hydrogen annealing, and may be convex, or concave. The DRAM further comprising a collar oxide extending into the shallow trench isolation region on the second side.

    摘要翻译： 一种用于DRAM器件的方法和结构，其包括绝缘体内的沟槽，沟槽内的导体，与沟槽的第一侧相邻的晶体管，以及形成在第二侧的导体的顶部内的浅沟槽隔离区 所述沟槽的第一侧相对，其中所述导体的顶部在所述浅沟槽隔离区域的边缘处具有弯曲形状。 弯曲形状包括导电带并且电连接导体和形成晶体管的单晶，还包括围绕导体顶部的环形氧化物，该环形氧化物控制弯曲形状的形状和位置。 弯曲形状由氢退火形成，并且可以是凸形或凹形。 DRAM还包括延伸到第二侧上的浅沟槽隔离区域的环状氧化物。

    Modified gate processing for optimized definition of array and logic devices on same chip
    9.
    发明授权
    Modified gate processing for optimized definition of array and logic devices on same chip 失效
    改进的门处理，用于在同一芯片上优化阵列和逻辑器件的定义

    公开(公告)号：US06403423B1

    公开(公告)日：2002-06-11

    申请号：US09713272

    申请日：2000-11-15

    申请人： Mary E. Weybright ,  Gary Bronner ,  Richard A. Conti ,  Ramachandra Divakaruni ,  Jeffrey Peter Gambino ,  Peter Hoh ,  Uwe Schroeder

    发明人： Mary E. Weybright ,  Gary Bronner ,  Richard A. Conti ,  Ramachandra Divakaruni ,  Jeffrey Peter Gambino ,  Peter Hoh ,  Uwe Schroeder

    IPC分类号： H01L21336

    CPC分类号： H01L27/10894 ,  H01L21/76897 ,  H01L21/823456 ,  H01L27/1052 ,  H01L27/10873

    摘要： Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made-smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.

    摘要翻译： 在阵列和支撑器件区域中使用两个不同的栅极导体电介质盖，使得可以在阵列区域中制造位线接触，但是可以使用较薄的硬掩模用于支撑装置区域中的更好的线宽控制。 在支撑掩模蚀刻期间，将较薄的介质盖制成阵列器件区域中的电介质间隔物。 这些电介质间隔物允许阵列栅极导体抗蚀剂线被制成 - 小于最终的栅极导体线宽。 这扩大了阵列栅极导体处理窗口。 第二电介质盖层改善了支撑装置和阵列装置的线宽控制。 在本发明中执行两个单独的栅极导体光刻步骤和栅极导体介电蚀刻，以优化阵列和支撑装置区域中的栅极导体线宽控制。 阵列和支撑装置区域中的栅极导体被同时蚀刻以降低生产成本。 在本发明的另外的实施例中，可以用包括无边界触点的阵列来制造具有或不具有自对准硅的双功能功能支撑器件晶体管。