公开(公告)号：US08895952B2

公开(公告)日：2014-11-25

申请号：US13404678

申请日：2012-02-24

申请人： Shigeki Kobayashi ,  Kazuhiko Yamamoto ,  Kenji Aoyama ,  Shigeto Oshino ,  Kei Watanabe ,  Shinichi Nakao ,  Satoshi Ishikawa ,  Takeshi Yamaguchi

发明人： Shigeki Kobayashi ,  Kazuhiko Yamamoto ,  Kenji Aoyama ,  Shigeto Oshino ,  Kei Watanabe ,  Shinichi Nakao ,  Satoshi Ishikawa ,  Takeshi Yamaguchi

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L27/2481 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/149

摘要： A nonvolatile storage device is formed by laminating a plurality of memory cell arrays, the memory cell array including a plurality of word lines, a plurality of bit lines, and memory cells. The memory cell includes a current rectifying device and a variable resistance device, the variable resistance device includes a lower electrode, an upper electrode, and a resistance change layer including a conductive nano material formed between the lower electrode and the upper electrode, one of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the lower electrode serving as a cathode, the other of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the upper electrode serving as a cathode.

摘要翻译： 通过层叠多个存储单元阵列形成非易失性存储装置，所述存储单元阵列包括多个字线，多个位线和存储单元。 存储单元包括电流整流装置和可变电阻装置，可变电阻装置包括下电极，上电极和包括形成在下电极和上电极之间的导电纳米材料的电阻变化层， 在层叠方向上彼此相邻设置的可变电阻装置在电阻变化层和作为阴极的下部电极之间具有钛氧化物（TiOx），另外在层叠方向上彼此相邻设置的可变电阻装置具有钛 电阻变化层和作为阴极的上部电极之间的氧化物（TiOx）。

公开(公告)号：US08512827B2

公开(公告)日：2013-08-20

申请号：US13168108

申请日：2011-06-24

申请人： Kenichi Seguchi ,  Kazuhiko Yamamoto

发明人： Kenichi Seguchi ,  Kazuhiko Yamamoto

IPC分类号： B41M5/00 ,  B41M5/52 ,  B41M5/50

CPC分类号： B41M5/52 ,  B41M5/506 ,  B41M5/508 ,  B41M5/5218 ,  B41M5/5236 ,  B41M5/5254 ,  B41M5/5281 ,  B41M5/529

摘要： Provided is an ink jet recording medium which is capable of reproducing a wide range of gloss including high luster like metallic luster and substantially no luster due to matting by varying only the amount of applied ink and in which the consumption of a white ink used to adjust the glossiness thereof is small.

摘要翻译： 本发明提供一种喷墨记录介质，其能够再现宽范围的光泽，其包括如光泽度高的光泽，并且由于仅通过改变所施加的油墨的量而消光而基本上没有光泽，并且其中用于调节的白色油墨的消耗 其光泽度小。

公开(公告)号：US08416603B2

公开(公告)日：2013-04-09

申请号：US12973064

申请日：2010-12-20

申请人： Kenji Aoyama ,  Kazuhiko Yamamoto

发明人： Kenji Aoyama ,  Kazuhiko Yamamoto

IPC分类号： G11C11/00 ,  H01L45/00

CPC分类号： B82Y30/00 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/149

摘要： According to one embodiment, a nonvolatile memory device includes a first conductive member and a second conductive member. The first conductive member extends in a first direction. The second conductive member extends in a second direction intersecting the first direction. A portion of the first conductive member connected to the second conductive member protrudes toward the second conductive member. A resistivity of the first conductive member in the first direction is lower than a resistivity of the first conductive member in a third direction of the protrusion of the first conductive member. A resistance value of the first conductive member in the third direction changes. A resistivity of the second conductive member in the second direction is lower than a resistivity of the second conductive member in the third direction. A resistance value of the second conductive member in the third direction changes.

摘要翻译： 根据一个实施例，非易失性存储器件包括第一导电构件和第二导电构件。 第一导电构件沿第一方向延伸。 第二导电构件沿与第一方向相交的第二方向延伸。 连接到第二导电构件的第一导电构件的一部分朝向第二导电构件突出。 第一导电构件在第一方向上的电阻率低于第一导电构件在第一导电构件的突起的第三方向上的电阻率。 第一导电构件在第三方向上的电阻值改变。 第二导电构件在第二方向上的电阻率低于第二导电构件在第三方向上的电阻率。 第二导电构件在第三方向上的电阻值改变。

公开(公告)号：US08379431B2

公开(公告)日：2013-02-19

申请号：US13043923

申请日：2011-03-09

申请人： Shigeki Kobayashi ,  Kazuhiko Yamamoto

发明人： Shigeki Kobayashi ,  Kazuhiko Yamamoto

IPC分类号： G11C11/00

CPC分类号： G11C16/0466 ,  G11C16/10 ,  G11C16/3418

摘要： A memory cell array includes memory transistors each including a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, and a variable resistance film formed on the gate electrode and made of a variable resistance material having variable resistance and is configured by plural memory strings disposed with longer direction extending in a first direction and including plural series-connected memory transistors. Word lines are disposed with a longer direction extending in a second direction orthogonal to the first direction, and connected commonly to the gate electrodes of the plural memory transistors lined up in the second direction. A plate line is disposed to sandwich the variable resistance film with the gate electrode. First voltage terminals supply a certain voltage to first ends of the plural memory strings. Second voltage terminals supply a certain voltage to second ends of the plural memory strings.

摘要翻译： 存储单元阵列包括存储晶体管，每个存储晶体管包括形成在半导体衬底上的栅极绝缘膜，形成在栅极绝缘膜上的栅电极和形成在栅极上的可变电阻膜，并且由可变电阻材料制成， 由沿着第一方向延伸的包括多个串联存储晶体管的长方向布置的多个存储器串构成。 字线沿着与第一方向正交的第二方向延伸的较长方向布置，并且共同连接到沿第二方向排列的多个存储晶体管的栅电极。 设置板线以与栅电极夹住可变电阻膜。 第一电压端子向多个存储器串的第一端提供一定电压。 第二电压端子向多个存储器串的第二端提供一定电压。

公开(公告)号：US08211812B2

公开(公告)日：2012-07-03

申请号：US12104353

申请日：2008-04-16

申请人： Lars-Ake Ragnarsson ,  Paul Zimmerman ,  Kazuhiko Yamamoto ,  Tom Schram ,  Wim Deweerd ,  David Brunco ,  Stefan De Gendt ,  Wilfried Vandervorst

发明人： Lars-Ake Ragnarsson ,  Paul Zimmerman ,  Kazuhiko Yamamoto ,  Tom Schram ,  Wim Deweerd ,  David Brunco ,  Stefan De Gendt ,  Wilfried Vandervorst

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/316 ,  C23C16/56 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31604 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

摘要： One inventive aspect relates to a method for fabricating a high-k dielectric layer. The method comprises depositing onto a substrate a layer of a high-k dielectric material having a first thickness. The high-k dielectric material has a bulk density value and the first thickness is so that the high-k dielectric layer has a density of at least the bulk density value of the high-k dielectric material minus about 10%. The method further comprises thinning the high-k dielectric layer to a second thickness. Another inventive aspect relates to a semiconductor device comprising a high-k dielectric layer as fabricated by the method.

摘要翻译： 本发明的一个方面涉及一种用于制造高k电介质层的方法。 该方法包括在基底上沉积具有第一厚度的高k电介质材料的层。 高k电介质材料具有体积密度值，第一厚度使得高k电介质层具有至少高k电介质材料的体积密度值减去约10％的密度。 该方法还包括将高k电介质层变薄至第二厚度。 另一个发明方面涉及包括通过该方法制造的高k电介质层的半导体器件。

公开(公告)号：US20120025159A1

公开(公告)日：2012-02-02

申请号：US12973064

申请日：2010-12-20

申请人： Kenji AOYAMA ,  Kazuhiko Yamamoto

发明人： Kenji AOYAMA ,  Kazuhiko Yamamoto

IPC分类号： H01L45/00 ,  B82Y99/00

CPC分类号： B82Y30/00 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/149

摘要： According to one embodiment, a nonvolatile memory device includes a first conductive member and a second conductive member. The first conductive member extends in a first direction. The second conductive member extends in a second direction intersecting the first direction. A portion of the first conductive member connected to the second conductive member protrudes toward the second conductive member. A resistivity of the first conductive member in the first direction is lower than a resistivity of the first conductive member in a third direction of the protrusion of the first conductive member. A resistance value of the first conductive member in the third direction changes. A resistivity of the second conductive member in the second direction is lower than a resistivity of the second conductive member in the third direction. A resistance value of the second conductive member in the third direction changes.

摘要翻译： 根据一个实施例，非易失性存储器件包括第一导电构件和第二导电构件。 第一导电构件沿第一方向延伸。 第二导电构件沿与第一方向相交的第二方向延伸。 连接到第二导电构件的第一导电构件的一部分朝向第二导电构件突出。 第一导电构件在第一方向上的电阻率低于第一导电构件在第一导电构件的突起的第三方向上的电阻率。 第一导电构件在第三方向上的电阻值改变。 第二导电构件在第二方向上的电阻率低于第二导电构件在第三方向上的电阻率。 第二导电构件在第三方向上的电阻值改变。

公开(公告)号：US20110235395A1

公开(公告)日：2011-09-29

申请号：US13043923

申请日：2011-03-09

申请人： Shigeki KOBAYASHI ,  Kazuhiko Yamamoto

发明人： Shigeki KOBAYASHI ,  Kazuhiko Yamamoto

IPC分类号： G11C11/34

CPC分类号： G11C16/0466 ,  G11C16/10 ,  G11C16/3418

摘要： A memory cell array includes memory transistors each including a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, and a variable resistance film formed on the gate electrode and made of a variable resistance material having variable resistance and is configured by plural memory strings disposed with longer direction extending in a first direction and including plural series-connected memory transistors. Word lines are disposed with a longer direction extending in a second direction orthogonal to the first direction, and connected commonly to the gate electrodes of the plural memory transistors lined up in the second direction. A plate line is disposed to sandwich the variable resistance film with the gate electrode. First voltage terminals supply a certain voltage to first ends of the plural memory strings. Second voltage terminals supply a certain voltage to second ends of the plural memory strings.

摘要翻译： 存储单元阵列包括存储晶体管，每个存储晶体管包括形成在半导体衬底上的栅极绝缘膜，形成在栅极绝缘膜上的栅电极和形成在栅极上的可变电阻膜，并且由可变电阻材料制成， 由沿着第一方向延伸的包括多个串联存储晶体管的长方向布置的多个存储器串构成。 字线沿着与第一方向正交的第二方向延伸的较长方向布置，并且共同连接到沿第二方向排列的多个存储晶体管的栅电极。 设置板线以与栅电极夹住可变电阻膜。 第一电压端子向多个存储器串的第一端提供一定电压。 第二电压端子向多个存储器串的第二端提供一定电压。

公开(公告)号：US07820772B2

公开(公告)日：2010-10-26

申请号：US10594594

申请日：2005-03-30

申请人： Taketoshi Usui ,  Kazuhiko Yamamoto ,  Hisanao Yamamoto ,  Kazuhiro Daikai

发明人： Taketoshi Usui ,  Kazuhiko Yamamoto ,  Hisanao Yamamoto ,  Kazuhiro Daikai

IPC分类号： C08L63/00 ,  C08G59/18 ,  C08G59/50 ,  B32B27/38

CPC分类号： C08G59/184 ,  C08G59/18

摘要： An amine hardener for epoxy resins which comprises an amine adduct (A) and a low-molecular amine compound (B) as major components, wherein the molecular weight distribution of the amine adduct (A), which is defined by the ratio of the weight-average molecular weight to the number-average molecular weight, is 3 or lower and the low-molecular amine compound (B) is contained in an amount of 0.001 to 1 part by mass per 100 parts by mass of the amine adduct (A).

摘要翻译： 用于环氧树脂的胺固化剂，其包含胺加合物（A）和低分子胺化合物（B）作为主要组分，其中胺加合物（A）的分子量分布由重量比 平均分子量相对于数均分子量为3以下，低分子量胺化合物（B）的含量相对于100质量份胺加成物（A）为0.001〜1质量份， 。

公开(公告)号：US07727911B2

公开(公告)日：2010-06-01

申请号：US12349192

申请日：2009-01-06

申请人： Kenji Yoneda ,  Kazuhiko Yamamoto

发明人： Kenji Yoneda ,  Kazuhiko Yamamoto

IPC分类号： H01L21/31

CPC分类号： H01L29/517 ,  C23C16/40 ,  C23C16/45531 ,  H01L21/02148 ,  H01L21/02156 ,  H01L21/02161 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02192 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0228 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/3141 ,  H01L21/31608 ,  H01L21/31645 ,  H01L29/513

摘要： In formation of a gate insulating film made of a high dielectric constant metal silicate, atomic layer deposition (ALD) is performed by setting exposure time to a precursor containing a metal or the like to saturation time of a deposition rate by a surface adsorption reaction and by setting exposure time to an oxidizing agent to time required for a composition of a metal oxide film to reach 97% or more of a stoichiometric value.

摘要翻译： 在由高介电常数金属硅酸盐形成的栅极绝缘膜的形成中，通过将表面吸附反应的沉积速率的饱和时间设定为含有金属等的前体的曝光时间，进行原子层析出（ALD）， 通过将氧化剂的曝光时间设定为金属氧化物膜的组成所需的时间达到化学计量值的97％以上。

公开(公告)号：US07722726B2

公开(公告)日：2010-05-25

申请号：US10599482

申请日：2005-03-31

申请人： Kazumasa Shintani ,  Ryo Murakami ,  Kazuhiko Yamamoto

发明人： Kazumasa Shintani ,  Ryo Murakami ,  Kazuhiko Yamamoto

IPC分类号： H01F1/053

CPC分类号： C22C33/02 ,  B22D11/0651 ,  B22F1/0055 ,  B22F2998/00 ,  B22F2998/10 ,  B22F2999/00 ,  C22C1/0441 ,  C22C38/005 ,  H01F1/0577 ,  H01F41/0266 ,  B22F9/04 ,  B22F3/02 ,  B22F3/10 ,  B22F9/06 ,  B22F9/002 ,  B22F2207/07

摘要： The invention provides a method for producing alloy flakes for rare earth sintered magnets, which makes uniform the intervals, size, orientation, and shape of the R-rich region and the dendrites of the 2-14-1 phase, which inhibits formation of chill, and which produces flakes that are pulverized into powder of a uniform particle size in the pulverization step in the production of a rare earth sintered magnet, and that are pulverized into powder compactable into a product with a controlled shrink ratio, and alloy flakes for a rare earth sintered magnet obtained by the method, and a rare earth sintered magnet having excellent magnetic properties. The present method includes preparing an alloy melt of a composition consisting of R of rare earth metal elements and the balance M including B and Fe, and supplying and solidifying the alloy melt on a cooling roll, wherein the roll has on its surface linear nucleation inhibiting portions for inhibiting formation of dendrites or the like, and nucleating portions for formation of the dendrites, and wherein the inhibiting portions have a region with a width of more than 100 μm.

摘要翻译： 本发明提供一种制备稀土烧结磁体的合金薄片的方法，其使得富含R区的间隔，尺寸，取向和形状均匀，从而抑制2-14-1相的树突，从而抑制冷却 并且在制造稀土烧结磁体的粉碎步骤中产生粉碎成均匀粒径的粉末，并将其粉碎成可压缩成具有可控收缩率的产品的粉末，以及用于 通过该方法获得的稀土类烧结磁体和具有优异磁性的稀土类烧结磁体。 本发明的方法包括制备由稀土金属元素的R组成的组合物和包括B和Fe的余量M的合金熔体，并且在冷却辊上提供和固化合金熔体，其中该辊在其表面上具有线性成核抑制 用于抑制枝晶等的形成的部分，以及用于形成枝晶的成核部分，其中抑制部分具有宽度大于100μm的区域。