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343 条记录 (耗时 0.072 秒)

    Nonvolatile semiconductor memory device
    71.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US08223558B2

    公开(公告)日：2012-07-17

    申请号：US13179714

    申请日：2011-07-11

    申请人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Riichiro Shirota ,  Fumitaka Arai ,  Susumu Fujimura

    发明人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Riichiro Shirota ,  Fumitaka Arai ,  Susumu Fujimura

    IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/345 ,  G11C16/3454 ,  G11C16/3459 ,  G11C16/3463 ,  G11C2211/5621

    摘要： A NAND cell unit includes memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in an erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of a selected memory cell, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

    摘要翻译： NAND单元单元包括串联连接的存储单元。 对所有存储单元进行擦除操作。 然后，将与擦除操作中施加的擦除电压极性相反的软编程电压施加到所有存储单元，从而将所有存储单元设置为过擦除状态。 此后，将20V的编程电压施加到所选择的存储单元的控制栅极，将0V施加到与所选存储单元相邻设置的两个存储单元的控制栅极，并且将11V施加到其余的控制栅极 记忆细胞 因此数据被编程到所选择的存储单元中。 根据要编程到所选择的存储单元中的数据来调整对所选存储单元施加编程电压的时间。 因此，可以将数据“0”正确地编程到所选择的存储单元中，可以从任何选择的存储单元高速读取多值数据。

    Nonvolatile Semiconductor Memory Device
    73.
    发明申请
    Nonvolatile Semiconductor Memory Device 有权
    非易失性半导体存储器件

    公开(公告)号：US20080062764A1

    公开(公告)日：2008-03-13

    申请号：US11929210

    申请日：2007-10-30

    申请人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Riichiro Shirota ,  Fumitaka Arai ,  Susumu Fujimura

    发明人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Riichiro Shirota ,  Fumitaka Arai ,  Susumu Fujimura

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/345 ,  G11C16/3454 ,  G11C16/3459 ,  G11C16/3463 ,  G11C2211/5621

    摘要： A NAND cell unit includes memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in an erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of a selected memory cell, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

    摘要翻译： NAND单元单元包括串联连接的存储单元。 对所有存储单元进行擦除操作。 然后，将与擦除操作中施加的擦除电压极性相反的软编程电压施加到所有存储单元，从而将所有存储单元设置为过擦除状态。 此后，将20V的编程电压施加到所选择的存储单元的控制栅极，将0V施加到与所选存储单元相邻设置的两个存储单元的控制栅极，并且将11V施加到其余的控制栅极 记忆细胞 因此数据被编程到所选择的存储单元中。 根据要编程到所选择的存储单元中的数据来调整对所选存储单元施加编程电压的时间。 因此，可以将数据“0”正确地编程到所选择的存储单元中，可以从任何选择的存储单元高速读取多值数据。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    75.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
    半导体集成电路设备

    公开(公告)号：US20070076494A1

    公开(公告)日：2007-04-05

    申请号：US11533061

    申请日：2006-09-19

    申请人： Ken Takeuchi ,  Tomoharu Tanaka

    发明人： Ken Takeuchi ,  Tomoharu Tanaka

    IPC分类号： G11C29/00

    CPC分类号： G11C7/12 ,  G11C7/18 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2207/002 ,  G11C2211/5621

    摘要： A semiconductor integrated circuit device includes a memory cell section containing memory cells, bit lines connected to one end of the memory cell section, and a data circuit connected to the bit lines to temporarily store one of write data and read data with respect to the memory cell. Each of the bit lines includes N sub-bit lines and (N-1) transfer gate portions. Each of the transfer gate portions includes a selection transistor.

    摘要翻译： 半导体集成电路装置包括存储单元部分，其包含存储单元，连接到存储单元部分的一端的位线和连接到位线的数据电路，以临时存储相对于存储器的写数据和读数据之一 细胞。 每个位线包括N个子位线和（N-1）个传输门部分。 每个传输门部分包括选择晶体管。

    Fail number detecting circuit of flash memory
    77.
    发明授权
    Fail number detecting circuit of flash memory 有权
    闪存的故障号检测电路

    公开(公告)号：US06859401B2

    公开(公告)日：2005-02-22

    申请号：US10674404

    申请日：2003-10-01

    申请人： Koji Hosono ,  Tamio Ikehashi ,  Tomoharu Tanaka ,  Kenichi Imamiya ,  Hiroshi Nakamura ,  Ken Takeuchi

    发明人： Koji Hosono ,  Tamio Ikehashi ,  Tomoharu Tanaka ,  Kenichi Imamiya ,  Hiroshi Nakamura ,  Ken Takeuchi

    IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/34 ,  G11C29/04 ,  G11C29/12

    CPC分类号： G11C16/3445 ,  G11C16/3436 ,  G11C16/3459

    摘要： A semiconductor device includes a memory cell array, latch circuits, first to third circuits and a current control circuit. The memory cell array includes NAND cells arranged therein. The latch circuits temporarily hold data read out from the memory cell array. The first circuit generates a first current varying in proportion to “1” or “0” of binary logic data of one end of the plurality of latch circuits. The second circuit generates a second current which is preset. The third circuit compares the first current with the second current. The value of “1” or “0” of binary logic data of the one end of the plurality of latch circuits is detected based on a result of the comparison between the first current and the second current.

    摘要翻译： 半导体器件包括存储单元阵列，锁存电路，第一至第三电路和电流控制电路。 存储单元阵列包括其中布置的NAND单元。 锁存电路暂时保存从存储单元阵列读出的数据。 第一电路产生与多个锁存电路的一端的二进制逻辑数据的“1”或“0”成比例变化的第一电流。 第二电路产生预置的第二电流。 第三电路将第一电流与第二电流进行比较。 基于第一电流和第二电流之间的比较结果，检测多个锁存电路一端的二进制逻辑数据的“1”或“0”值。

    Fail number detecting circuit of flash memory
    78.
    发明授权
    Fail number detecting circuit of flash memory 有权
    闪存的故障号检测电路

    公开(公告)号：US06657896B2

    公开(公告)日：2003-12-02

    申请号：US10315050

    申请日：2002-12-10

    申请人： Koji Hosono ,  Tamio Ikehashi ,  Tomoharu Tanaka ,  Kenichi Imamiya ,  Hiroshi Nakamura ,  Ken Takeuchi

    发明人： Koji Hosono ,  Tamio Ikehashi ,  Tomoharu Tanaka ,  Kenichi Imamiya ,  Hiroshi Nakamura ,  Ken Takeuchi

    IPC分类号： G11C1606

    CPC分类号： G11C16/3445 ,  G11C16/3436 ,  G11C16/3459

    摘要： A semiconductor memory device includes a memory cell array, latch circuits, first to third circuits and a current control circuit. The memory cell array includes electrically rewritable nonvolatile memory cells arranged therein. The latch circuits temporarily hold data read out from the memory cell array. The first circuit generates a first current which varies in proportion to “1” or “0” of binary logical data of one end of the latch circuits. The second circuit generates a predetermined second current. The current control circuit is connected to the first and second circuits, and configured to determined absolute values of the first and second currents. The third circuit is configured to compare the first and second currents. The number of binary logical data of “1” or “0” of one end of the latch circuits is detected based on the result of comparison between the first and second currents.

    摘要翻译： 半导体存储器件包括存储单元阵列，锁存电路，第一至第三电路和电流控制电路。 存储单元阵列包括布置在其中的电可重写非易失性存储单元。 锁存电路暂时保存从存储单元阵列读出的数据。 第一电路产生与锁存电路的一端的二进制逻辑数据的“1”或“0”成比例变化的第一电流。 第二电路产生预定的第二电流。 电流控制电路连接到第一和第二电路，并被配置为确定第一和第二电流的绝对值。 第三电路被配置为比较第一和第二电流。 基于第一和第二电流之间的比较结果来检测锁存电路的一端的“1”或“0”的二进制逻辑数据的数量。

    Nonvolatile semiconductor memory device
    80.
    发明授权
    Nonvolatile semiconductor memory device 有权

    公开(公告)号：US06434055B1

    公开(公告)日：2002-08-13

    申请号：US09767152

    申请日：2001-01-23

    申请人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Riichiro Shirota ,  Fumitaka Arai ,  Susumu Fujimura

    发明人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Riichiro Shirota ,  Fumitaka Arai ,  Susumu Fujimura

    IPC分类号： G11C1604

    摘要： A NAND cell unit comprising a plurality of memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in the erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of any selected one of the memory cells, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.