公开(公告)号：US09111603B1

公开(公告)日：2015-08-18

申请号：US13409077

申请日：2012-02-29

申请人： Xiaobao Wang ,  Chiakang Sung ,  Joseph Huang

发明人： Xiaobao Wang ,  Chiakang Sung ,  Joseph Huang

IPC分类号： G11C5/14

CPC分类号： G11C5/147 ,  G11C5/14

摘要： An integrated circuit may include a memory controller that interfaces with memory via one or more ports. A given port may be coupled to a comparator that receives data signals from the memory and a reference voltage signal and produces a corresponding output signal that identifies whether the data signals are logic one signals or logic zero signals. The memory controller may include detection circuitry coupled to the port that produces a target reference voltage signal for calibration of the reference voltage signal. The memory controller may include circuitry that produces the reference voltage signal based on control signals received from control circuitry. The control circuitry may generate the control signals to calibrate the reference voltage signal based on the target reference voltage.

摘要翻译： 集成电路可以包括经由一个或多个端口与存储器接口的存储器控​​制器。 给定端口可以耦合到从存储器接收数据信号的比较器和参考电压信号，并产生相应的输出信号，其识别数据信号是逻辑一个信号还是逻辑零信号。 存储器控制器可以包括耦合到端口的检测电路，其产生用于校准参考电压信号的目标参考电压信号。 存储器控制器可以包括基于从控制电路接收的控制信号产生参考电压信号的电路。 控制电路可以产生控制信号，以基于目标参考电压来校准参考电压信号。

公开(公告)号：US07221193B1

公开(公告)日：2007-05-22

申请号：US11040048

申请日：2005-01-20

申请人： Xiaobao Wang ,  Tzung-Chin Chang ,  Chiakang Sung ,  Khai Q. Nguyen

发明人： Xiaobao Wang ,  Tzung-Chin Chang ,  Chiakang Sung ,  Khai Q. Nguyen

IPC分类号： H03B1/00

CPC分类号： H03K19/0005 ,  H04L25/0298

摘要： Techniques are provided for controlling an on-chip termination resistance in an input or output (IO) buffer using calibration circuits. Each calibration circuit monitors the voltage between an external resistor and a group of on-chip transistors. When the effective resistance of the group of transistors matches the external resistance, the calibration circuit causes the effective resistance of drive transistors in the IO buffer to match the effective resistance of the group of on-chip transistors.

摘要翻译： 提供了使用校准电路来控制输入或输出（IO）缓冲器中的片上终端电阻的技术。 每个校准电路监视外部电阻和片上晶体管组之间的电压。 当晶体组的有效电阻与外部电阻相匹配时，校准电路使得IO缓冲器中的驱动晶体管的有效电阻与片上晶体管组的有效电阻相匹配。

公开(公告)号：US07825682B1

公开(公告)日：2010-11-02

申请号：US12147403

申请日：2008-06-26

申请人： Xiaobao Wang ,  Chiakang Sung ,  Khai Q. Nguyen ,  Sanjay K. Charagulla

发明人： Xiaobao Wang ,  Chiakang Sung ,  Khai Q. Nguyen ,  Sanjay K. Charagulla

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K19/0005 ,  H03K17/005 ,  H03K17/145 ,  H03K17/6871 ,  H03K17/6872 ,  H03K17/693

摘要： Techniques are provided for individually adjusting the on-chip termination impedance that is generated by input and output (IO) buffers in an input/output (IO) bank on an integrated circuit. The IO buffers in an IO bank can generate different on-chip termination impedances. And as a result, an IO bank can support more than one class of memory interfaces. An OCT calibration block generates a digital on-chip termination (OCT) calibration code. In some embodiments, circuitry in the IO banks can be configured to shift the OCT calibration code by one or more bits to adjust the series and/or parallel on-chip termination impedance in one or more IO buffers.

摘要翻译： 提供了用于单独调整由集成电路中的输入/输出（IO）组中的输入和输出（IO）缓冲器产生的片上终端阻抗的技术。 IO bank中的IO缓冲区可以产生不同的片上终端阻抗。 因此，IO bank可以支持多个类别的内存接口。 OCT校准块产生数字片上终端（OCT）校准码。 在一些实施例中，IO组中的电路可被配置为将OCT校准码移位一个或多个位以调整一个或多个IO缓冲器中的串联和/或并行片上终端阻抗。

公开(公告)号：US07218155B1

公开(公告)日：2007-05-15

申请号：US11040343

申请日：2005-01-20

申请人： Tzung-Chin Chang ,  Xiaobao Wang ,  Henry Kim ,  Chiakang Sung ,  Khai Q. Nguyen ,  Bonnie Wang ,  Jeffrey Tyhach ,  Gopinath Rangan

发明人： Tzung-Chin Chang ,  Xiaobao Wang ,  Henry Kim ,  Chiakang Sung ,  Khai Q. Nguyen ,  Bonnie Wang ,  Jeffrey Tyhach ,  Gopinath Rangan

IPC分类号： H03B1/00

CPC分类号： H03K19/0005

摘要： Techniques are provided for controlling an on-chip termination resistance in an input or output (IO) buffer using a calibration circuit. The calibration circuit monitors the voltage between an external resistor and a group of on-chip transistors. When voltage between the external resistor and the group of transistors is within a selected range, the calibration circuit causes the effective resistance of the transistors to match the resistance of the external resistor as closely as possible. The calibration circuit enables another set of transistors in the IO buffer so that the effective on resistance of the transistors in the IO buffer closely match the resistance of the external resistor.

摘要翻译： 提供了使用校准电路控制输入或输出（IO）缓冲器中的片上终端电阻的技术。 校准电路监视外部电阻和片上晶体管组之间的电压。 当外部电阻和晶体管组之间的电压在选定范围内时，校准电路会使晶体管的有效电阻尽可能接近外部电阻的电阻。 校准电路使得IO缓冲器中的另一组晶体管能够使得IO缓冲器中的晶体管的有效导通电阻与外部电阻器的电阻紧密匹配。

公开(公告)号：US07420386B2

公开(公告)日：2008-09-02

申请号：US11381356

申请日：2006-05-02

申请人： Xiaobao Wang ,  Chiakang Sung ,  Khai Q. Nguyen

发明人： Xiaobao Wang ,  Chiakang Sung ,  Khai Q. Nguyen

IPC分类号： H03K17/16

CPC分类号： G11C7/1048 ,  G11C2207/2254 ,  H03H11/30 ,  H04L25/0278 ,  H04L25/0292

摘要： On-chip termination (OCT) calibration techniques are provided that support input/output (IO) banks on an integrated circuit (IC) using OCT controllers. The OCT controllers calibrate the on-chip termination impedance in the IO banks using a shared parallel bus or separate parallel buses. Multiplexers or select logic in each IO bank select control signals from the OCT controllers in response to select signals. According to some embodiments, each of the IO banks on an IC can receive OCT control signals from any of the OCT controllers on the IC.

摘要翻译： 提供使用OCT控制器在集成电路（IC）上支持输入/输出（IO）组的片上终止（OCT）校准技术。 OCT控制器使用共享并行总线或单独的并行总线校准IO组中的片上终端阻抗。 每个IO组中的多路复用器或选择逻辑根据选择信号选择来自OCT控制器的控制信号。 根据一些实施例，IC上的每个IO组可以从IC上的任何OCT控制器接收OCT控制信号。

公开(公告)号：US07417452B1

公开(公告)日：2008-08-26

申请号：US11462702

申请日：2006-08-05

申请人： Xiaobao Wang ,  Chiakang Sung ,  Khai Q. Nguyen ,  Sanjay K. Charagulla

发明人： Xiaobao Wang ,  Chiakang Sung ,  Khai Q. Nguyen ,  Sanjay K. Charagulla

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K19/0005 ,  H03K17/005 ,  H03K17/145 ,  H03K17/6871 ,  H03K17/6872 ,  H03K17/693

摘要： Techniques are provided for individually adjusting the on-chip termination impedance that is generated by input and output (IO) buffers in an input/output (IO) bank on an integrated circuit. The IO buffers in an IO bank can generate different on-chip termination impedances. And as a result, an IO bank can support more than one class of memory interfaces. An OCT calibration block generates a digital on-chip termination (OCT) calibration code. In some embodiments, circuitry in the IO banks can be configured to shift the OCT calibration code by one or more bits to adjust the series and/or parallel on-chip termination impedance in one or more IO buffers.

摘要翻译： 提供了用于单独调整由集成电路中的输入/输出（IO）组中的输入和输出（IO）缓冲器产生的片上终端阻抗的技术。 IO bank中的IO缓冲区可以产生不同的片上终端阻抗。 因此，IO bank可以支持多个类别的内存接口。 OCT校准块产生数字片上终端（OCT）校准码。 在一些实施例中，IO组中的电路可被配置为将OCT校准码移位一个或多个位以调整一个或多个IO缓冲器中的串联和/或并行片上终端阻抗。

公开(公告)号：US07239171B1

公开(公告)日：2007-07-03

申请号：US10798597

申请日：2004-03-10

申请人： Xiaobao Wang ,  Chiakang Sung

发明人： Xiaobao Wang ,  Chiakang Sung

IPC分类号： H03K17/16 ,  H03K19/03

CPC分类号： H04L25/0278

摘要： Techniques are provided for matching the characteristic impedance of different transmission lines coupled to I/O pins on an integrated circuit. On-chip termination impedance circuitry can generate different termination impedance values for each I/O pin. Each termination impedance value is selected to match the characteristic impedance of the transmission line coupled to a particular I/O pin. The termination impedance can be set in response to the value of an off-chip resistor. Bit shifter circuitry can change the termination impedance provided to individual I/O pins. The bit shifter circuitry can increase or decrease the termination impedance at any of the I/O pins without changing the value of the off-chip resistor.

摘要翻译： 提供技术用于匹配耦合到集成电路上的I / O引脚的不同传输线的特性阻抗。 片上终端阻抗电路可以为每个I / O引脚产生不同的终端阻抗值。 选择每个终端阻抗值以匹配耦合到特定I / O引脚的传输线的特性阻抗。 可以根据片外电阻的值来设置终端阻抗。 位移电路可以改变提供给各个I / O引脚的终端阻抗。 位移电路可以增加或减少任何I / O引脚的终端阻抗，而不改变片外电阻的值。

公开(公告)号：US20140313626A1

公开(公告)日：2014-10-23

申请号：US13867034

申请日：2013-04-20

申请人： Xiaobao Wang

发明人： Xiaobao Wang

IPC分类号： H02H9/04

CPC分类号： H02H9/04 ,  H02H7/1222 ,  H02H7/1227 ,  H02M1/32 ,  H02M3/1582

摘要： A programmable system includes a first level protection circuit comprised of discharge tube CR1/CR2 and piezoresistor MOV1/MOV2 in series; a second-level protection circuit comprised of the series arm of capacitor C1 and resistor R1 in parallel with a transient voltage suppression diode TVS1, and inductors L1/L2 connected to the ends of first level and second-level protection circuits respectively. A control circuit includes a PWM driver module and a SCM. The PWM driver module is connected to the PWM control port of the SCM and its output is connected to an IGBT module. The control circuit is also connected to a series communication module and to a user interface. The features of the invention are: strong-shock resistance; a wide range of load adaptability; and ability of accurately and steplessly regulating and adjusting with high frequency and high power load.

摘要翻译： 可编程系统包括串联的放电管CR1 / CR2和压控电阻MOV1 / MOV2组成的第一电平保护电路; 包括电容器C1的串联臂和与瞬态电压抑制二极管TVS1并联的电阻器R1的二级保护电路，以及分别连接到第一级和第二级保护电路两端的电感器L1 / L2。 控制电路包括PWM驱动器模块和SCM。 PWM驱动器模块连接到SCM的PWM控制端口，其输出连接到IGBT模块。 控制电路还连接到串行通信模块和用户接口。 本发明的特点是：抗冲击性强; 适应范围广泛; 以及高频，高功率负载下精确，无级调节调节的能力。

公开(公告)号：US07506296B1

公开(公告)日：2009-03-17

申请号：US11406929

申请日：2006-04-18

申请人： Zahir Parpia ,  Khai Q. Nguyen ,  Xiaobao Wang

发明人： Zahir Parpia ,  Khai Q. Nguyen ,  Xiaobao Wang

IPC分类号： G06F17/50

CPC分类号： G06F17/5054

摘要： A logic design system is provided for designing programmable logic device integrated circuits with minimized predriver power consumption. The logic design system identifies predriver circuits that can operate satisfactorily at reduced predriver power supply levels. One or more reduced predriver power supply levels for powering the predriver circuits are identified by the logic design system. The predriver power supply levels that are identified can be different than a maximum allowable power supply voltage used for powering input-output circuitry on the programmable logic device integrated circuit. There may be multiple blocks of predriver circuitry, each of which is powered using a potentially different predriver power supply voltage. The logic design system uses on-screen options to accept user-supplied settings related to minimizing predriver power consumption.

摘要翻译： 提供了一种用于设计可编程逻辑器件集成电路的逻辑设计系统，具有最小的预驱动器功耗。 逻辑设计系统识别能够以降低的预驱动电源电平令人满意地运行的预驱动电路。 用于为预驱动电路供电的一个或多个减少的预驱动电源电平由逻辑设计系统识别。 识别的预驱动电源电平可以与用于为可编程逻辑器件集成电路上的输入输出电路供电的最大允许电源电压不同。 可能有多个预驱动电路块，每个都使用潜在不同的预驱动电源电压供电。 逻辑设计系统使用屏幕选项来接受用户提供的设置，以最大限度地减少前驱功耗。