公开(公告)号：US6146960A

公开(公告)日：2000-11-14

申请号：US195744

申请日：1998-11-18

申请人： Kuang-Yeh Chang

发明人： Kuang-Yeh Chang

IPC分类号： H01L21/02 ,  H01L27/06 ,  H01L21/20 ,  H01L21/4763 ,  H01L21/8242

CPC分类号： H01L27/0629 ,  H01L28/40

摘要： A method of forming mixed mode devices is provided. A field oxide layer is formed on the substrate to isolate active regions from each other. A gate oxide layer is formed on the substrate, positioned over the active regions. A first conductive layer, a silicide layer and a second conductive layer are formed on the field oxide layer and on the gate oxide layer. The second conductive layer is converted to an oxide layer as a dielectric layer of a capacitor by thermal oxidation. A third conductive layer is formed and defined on the dielectric layer to form an upper electrode of the capacitor. A anisotropic etching step is performed to remove a part of the dielectric layer, a part of the silicide layer and a part of the first conductive layer to complete the capacitor and to form a gate of a transistor.

摘要翻译： 提供了一种形成混合模式装置的方法。 在衬底上形成场氧化物层以隔离有源区域。 栅极氧化层形成在衬底上，位于有源区上。 在场氧化物层和栅极氧化物层上形成第一导电层，硅化物层和第二导电层。 第二导电层通过热氧化转变为电容器的介电层的氧化物层。 在电介质层上形成并限定第三导电层以形成电容器的上电极。 执行各向异性蚀刻步骤以去除介电层的一部分，硅化物层的一部分和第一导电层的一部分以完成电容器并形成晶体管的栅极。

公开(公告)号：US6013574A

公开(公告)日：2000-01-11

申请号：US906062

申请日：1997-08-05

申请人： Fred N. Hause ,  Michael J. Gatto ,  Kuang-Yeh Chang

发明人： Fred N. Hause ,  Michael J. Gatto ,  Kuang-Yeh Chang

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/28 ,  H01L21/31

CPC分类号： H01L21/02063 ,  H01L21/31105 ,  H01L21/31138 ,  H01L21/76877

摘要： A method of forming low resistance contact structures in vias arranged between interconnect levels is provided. The method involves interconnect lines having an anti-reflective layer formed thereupon. An interlevel dielectric layer is formed over the interconnect lines. A photoresist layer is formed over the interlevel dielectric layer and patterned to define via locations. During via etch, an organic (carbon-based) polymer layer forms upon the anti-reflective-coated interconnect lines at the bottoms of the vias. The photoresist and the etch byproduct polymer layers are then removed using a dry etch process which employs a forming gas comprising nitrogen and hydrogen. A native oxide layer subsequently forms upon the anti-reflective-coated interconnect lines when exposed to oxygen. The native oxide layer is then removed, along with any residual etch byproduct polymer, during a sputter etch procedure. Each resulting via is substantially void of polymer and oxide residue so as to present a clean via area which allows ready adherence of a plug material to the anti-reflective coating.

摘要翻译： 提供了一种在布置在互连层之间的通孔中形成低电阻接触结构的方法。 该方法涉及在其上形成有抗反射层的互连线。 在互连线上形成层间电介质层。 在层间电介质层之上形成光致抗蚀剂层并图案化以限定通孔位置。 在通孔蚀刻期间，在通孔底部的抗反射涂覆的互连线上形成有机（碳基）聚合物层。 然后使用采用包含氮和氢的成形气体的干式蚀刻工艺除去光致抗蚀剂和蚀刻副产物聚合物层。 当暴露于氧气时，随后在抗反射涂布的互连线上形成天然氧化物层。 然后在溅射蚀刻过程期间将天然氧化物层与任何残留的蚀刻副产物聚合物一起除去。 每个所得到的通孔基本上不含聚合物和氧化物残余物，以便呈现干净的通孔区域，其允许插塞材料容易地粘附到抗反射涂层上。

公开(公告)号：US5904539A

公开(公告)日：1999-05-18

申请号：US619004

申请日：1996-03-21

申请人： Fred N. Hause ,  Robert Dawson ,  Charles E. May ,  Mark I. Gardner ,  Kuang-Yeh Chang

发明人： Fred N. Hause ,  Robert Dawson ,  Charles E. May ,  Mark I. Gardner ,  Kuang-Yeh Chang

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76229 ,  Y10S148/05

摘要： An isolation technique is provided for improving the overall planarity of filled isolation regions relative to adjacent silicon mesas. The isolation process results in a silicon mesa having enhanced mechanical and electrical properties. Planarity is performed by repeating the steps of filling isolation trenches, patterning large area isolation trenches, and refilling isolation trenches to present an upper surface having indents which can be readily removed by a chemical-mechanical polish. The silicon mesa upper surface is enhanced by utilizing a unique set of layers stacked upon the silicon substrate, and thereafter patterning the substrate to form raised silicon surfaces, or mesas, having the stacked layers thereon. The patterned, stacked layers include a unique combination of dissimilar compositions which, when removed, leave a silicon mesa upper surface which is recessed below the adjacent, filled trenches. The patterned stacked layers incorporate a polysilicon and/or oxide buffer which prevents deleterious migration of nitrogen from the overlying nitride layer to the underlying silicon mesa upper surface.

摘要翻译： 提供隔离技术用于改善填充隔离区相对于相邻硅台面的整体平面度。 隔离过程产生具有增强的机械和电性能的硅台面。 通过重复填充隔离沟槽，图案化大面积隔离沟槽和重新填充隔离沟槽以呈现具有可以通过化学机械抛光容易去除的凹痕的上表面的步骤来执行平面度。 通过利用堆叠在硅衬底上的独特的一组层来增强硅台面上表面，然后对衬底进行图案化以形成其上具有堆叠层的凸起的硅表面或台面。 图案化的堆叠层包括不同组合物的独特组合，当被去除时，其离开相邻填充沟槽下方的硅台面上表面。 图案化的堆叠层包含多晶硅和/或氧化物缓冲液，其可防止氮从上覆的氮化物层到底层的硅台面上表面的有害迁移。

公开(公告)号：US5831894A

公开(公告)日：1998-11-03

申请号：US103958

申请日：1998-06-24

申请人： Kuang-Yeh Chang

发明人： Kuang-Yeh Chang

IPC分类号： G11C16/04 ,  H01L27/115 ,  G11C17/00

CPC分类号： H01L27/115 ,  G11C16/0491

摘要： The read only memory includes a number of word lines and a number of bit lines. The word lines and the bit lines are arranged in a matrix. Between every two of the bit lines and on every word line there forms a memory cell. The two bit lines of the memory cell are a first bit line and a second bit line. The method of programming includes the following steps. The first bit line is supplied with a first voltage. The second bit line is supplied with a second voltage. The word line is supplied with a third voltage. Bit lines at the same side of the first bit line are supplied with the first voltage. Bit lines at the same side of the second bit line are supplied with the second voltage.

摘要翻译： 只读存储器包括多个字线和多个位线。 字线和位线被排列成矩阵。 在每两个位线和每个字线之间形成一个存储单元。 存储单元的两个位线是第一位线和第二位线。 编程方法包括以下步骤。 第一位线被提供有第一电压。 第二位线被提供有第二电压。 字线被提供有第三电压。 在第一位线的同一侧的位线被提供第一电压。 在第二位线的同一侧的位线被提供有第二电压。

公开(公告)号：US5750428A

公开(公告)日：1998-05-12

申请号：US722799

申请日：1996-09-27

申请人： Kuang-Yeh Chang

发明人： Kuang-Yeh Chang

IPC分类号： H01L21/336

CPC分类号： H01L29/66825

摘要： A method of fabricating a novel electrically erasable programmable read only memory (EEPROM) cell for use in semiconductor memories is disclosed herein. Since the degree of ion implantation in the substrate determines the thichness of the silicon dioxide. The proper thickness of the silicon dioxide can be determined by considering the particular dopant to be used and degree of ion implantation, a 50-100 angstroms silicon dioxide is chosen for an arsenic or phosphorus dopant, 1E14-1E15 atoms/cm.sup.2, 100 KeV, ion implantation. A 150-350 angstroms silicon dioxide is chosen for an arsenic or phosphorus dopant, 1E11-1E13 atoms/cm.sup.2, 100 KeV, ion implantation. The method includes the steps of: forming an isolation layer on a substrate to serve as an isolation; doping ions to form a lightly-doped region in the substrate; patterning a photoresist on the substrate; doping an ions to form a highly-doped region in the substrate; removing the photoresist; oxidizing the substrate to form a gate oxide and a tunnel oxide simultaneously; and forming a first polysilicon layer on the gate oxide and the tunnel oxide.

摘要翻译： 本文公开了制造用于半导体存储器的新型电可擦除可编程只读存储器（EEPROM）单元的方法。 由于衬底中的离子注入程度决定了二氧化硅的亮度。 二氧化硅的适当厚度可以通过考虑使用的特定掺杂剂和离子注入度来确定，对于砷或磷掺杂剂选择50-100埃的二氧化硅，1E14-1E15原子/ cm2，100KeV， 离子注入。 对于砷或磷掺杂剂，选择150-350埃二氧化硅，1E11-1E13原子/ cm2，100KeV离子注入。 该方法包括以下步骤：在衬底上形成隔离层以用作隔离层; 掺杂离子以在衬底中形成轻掺杂区域; 在衬底上图案化光致抗蚀剂; 掺杂离子以在衬底中形成高掺杂区域; 去除光致抗蚀剂; 氧化衬底同时形成栅极氧化物和隧道氧化物; 以及在所述栅极氧化物和所述隧道氧化物上形成第一多晶硅层。

公开(公告)号：US5693568A

公开(公告)日：1997-12-02

申请号：US572317

申请日：1995-12-14

申请人： Yowjuang W. Liu ,  Kuang-Yeh Chang

发明人： Yowjuang W. Liu ,  Kuang-Yeh Chang

IPC分类号： H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76885

摘要： A reliable interconnection pattern is formed by depositing first and second conductive layers, etching to form a conductive pattern in the first conductive layer and etching to form an interconnection comprising a portion of the second conductive layer. Advantageously, the need to form openings in dielectric layers, and filling them with barrier materials and plugs, is avoided along with their attendant disadvantages. The resulting semiconductor device exhibits improved reliability, higher operating speeds and an improved signal-to-noise ratio.

摘要翻译： 通过沉积第一和第二导电层，蚀刻以在第一导电层中形成导电图案并进行蚀刻以形成包括第二导电层的一部分的互连来形成可靠的互连图案。 有利地，避免了需要在电介质层中形成开口并且填充阻挡材料和插塞以及其伴随的缺点。 所得到的半导体器件表现出改进的可靠性，更高的操作速度和更好的信噪比。

公开(公告)号：US5608253A

公开(公告)日：1997-03-04

申请号：US408613

申请日：1995-03-22

申请人： Yowjuang W. Liu ,  Kuang-Yeh Chang

发明人： Yowjuang W. Liu ,  Kuang-Yeh Chang

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/7832 ,  H01L21/823807 ,  H01L27/0928 ,  H01L29/1075 ,  H01L29/1087 ,  H01L29/6659 ,  Y10S257/901

摘要： A novel MOS transistor structure for improving device scaling by improving short channel control includes a buried back gate beneath a channel region of the MOS transistor. A separate contact to a well that is electrically communicated to the buried back gate improves short channel controls without performance degradations. In a preferred embodiment, the back gate is grounded when turning the n-channel MOS transistor off. In alternate embodiments, the buried layer produces retrograde p wells. In some applications, multiple buried layers may be used, with one or more being planar. CMOS devices may have independent, multiple buried back gates.

摘要翻译： 通过改善短沟道控制来提高器件缩放的新型MOS晶体管结构包括在MOS晶体管的沟道区下面的掩埋后栅极。 与通过电气传递到掩埋后门的阱的单独接触改善了短通道控制而没有性能下降。 在优选实施例中，当关闭n沟道MOS晶体管时，背栅极接地。 在替代实施例中，掩埋层产生逆行p阱。 在一些应用中，可以使用多个掩埋层，其中一个或多个是平面的。 CMOS器件可能具有独立的多重埋后栅。

公开(公告)号：US5565703A

公开(公告)日：1996-10-15

申请号：US415182

申请日：1995-04-03

申请人： Kuang-Yeh Chang

发明人： Kuang-Yeh Chang

IPC分类号： H01L23/525 ,  H01L29/00

CPC分类号： H01L23/5252 ,  H01L2924/0002

摘要： A multilevel antifuse structure characterized by a substrate, a first antifuse structure formed above the substrate, and a second antifuse structure formed above the first antifuse structure. The first antifuse structure preferably includes a first conductive layer, a first antifuse layer disposed over the first conductive layer, a first dielectric layer disposed over the first antifuse layer and provided with a first via hole, and a first conductive via formed within the first via hole. The second antifuse structure preferably includes a second conductive layer, a second antifuse layer disposed over the second conductive layer, a second dielectric layer disposed over the second antifuse layer and provided with a second via hole, and a second conductive via formed within the second via hole. Preferably, the first antifuse layer and the second antifuse layer are patterned into a plurality of antifuse regions which are either vertically aligned or vertically staggered with respect to each other. A method for making a multilevel antifuse structure in accordance with the present invention includes the steps of forming a first antifuse structure over a substrate, and forming a second antifuse structure over the first antifuse structure. In one embodiment, the first antifuse structure and the second antifuse structure are vertically aligned, and are interconnected in parallel. The parallel interconnection is preferably accomplished by tungsten vias formed by either a blanket tungsten deposition and subsequent etch-back, or by a selective tungsten deposition.

摘要翻译： 一种多层反熔丝结构，其特征在于基板，形成在基板上方的第一反熔丝结构，以及形成在第一反熔丝结构之上的第二反熔丝结构。 第一反熔丝结构优选地包括第一导电层，设置在第一导电层上的第一反熔丝层，设置在第一反熔丝层之上并设置有第一通孔的第一介电层，以及形成在第一通孔内的第一导电通孔 孔。 第二反熔丝结构优选地包括第二导电层，设置在第二导电层上的第二反熔丝层，设置在第二反熔丝层之上并设置有第二通孔的第二介电层，以及形成在第二通孔内的第二导电通孔 孔。 优选地，第一反熔丝层和第二反熔丝层被图案化成多个相对于彼此垂直对准或垂直交错的反熔丝区域。 根据本发明的制造多层反熔丝结构的方法包括以下步骤：在衬底上形成第一反熔丝结构，并在第一反熔丝结构上形成第二反熔丝结构。 在一个实施例中，第一反熔丝结构和第二反熔丝结构垂直对准，并联并联。 平行互连优选通过由覆盖钨沉积和随后的回蚀或通过选择性钨沉积形成的钨通孔来实现。

公开(公告)号：US4987465A

公开(公告)日：1991-01-22

申请号：US266223

申请日：1988-10-28

申请人： Steven W. Longcor ,  Kuang-Yeh Chang ,  Jih-Chang Lien ,  David M. Rogers

发明人： Steven W. Longcor ,  Kuang-Yeh Chang ,  Jih-Chang Lien ,  David M. Rogers

IPC分类号： H01L27/02

CPC分类号： H01L27/0259 ,  H01L27/0266

摘要： An ESD protection device for CMOS integrated circuit inputs is disclosed. Two clamp components, coupled by a current limiting device, couple the pad to the circuitry of the chip. The device prevents damage to the circuit from an ESD of approximately 8000 or more volts at an input terminal.

摘要翻译： 公开了一种用于CMOS集成电路输入的ESD保护装置。 通过限流装置耦合的两个钳位部件将焊盘耦合到芯片的电路。 该装置防止在输入端子处从约8000或更高电压的ESD损坏电路。

公开(公告)号：US4775642A

公开(公告)日：1988-10-04

申请号：US10257

申请日：1987-02-02

申请人： Kuang-Yeh Chang ,  Charles F. Hart ,  Yee-Chaung See

发明人： Kuang-Yeh Chang ,  Charles F. Hart ,  Yee-Chaung See

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L21/265

CPC分类号： H01L27/11526 ,  H01L21/28273 ,  H01L27/11546

摘要： Implementing modified souce/drain implants in a non-volatile memory process while leaving the source/drain regions in the memory cells of the device unmodified and adding no critical mask steps. Methods for implementing both low dose drain and graded source/drain modifications in a double poly non-volatile memory process include the possibility of leaving the spacers used to modify the peripheral source/drain regions in place in the array portion of the device. Alternate methods include the possibility of removing the spacers in the array portion without the addition of critical mask steps and of keeping the spacers out of the array portion entirely.

摘要翻译： 在非易失性存储器过程中实现修改后的漏/漏注入，同时将源极/漏极区域保留在器件的存储器单元中，并且不会增加关键的掩模步骤。 在双重多元非易失性存储器处理中实现低剂量漏极和分级源极/漏极修改的方法包括留下用于将外围源极/漏极区域修改到器件的阵列部分中的适当位置的可能性。 替代方法包括在阵列部分中去除间隔物的可能性，而不增加临界掩模步骤并且将隔离物完全保持在阵列部分之外。