公开(公告)号：US20100271873A1

公开(公告)日：2010-10-28

申请号：US12830464

申请日：2010-07-06

申请人： Ki-Tae Park ,  Jung-Dal Choi ,  Sung-Kyu Jo

发明人： Ki-Tae Park ,  Jung-Dal Choi ,  Sung-Kyu Jo

IPC分类号： G11C16/06

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/24

摘要： A page buffer for a non-volatile semiconductor memory device includes a switch configured to couple a first bitline coupled to a first memory cell to a second bitline coupled to a second memory cell, a first latch block coupled to the first bitline and configured to transfer a first latch data to the first memory cell, and a second latch block coupled to the second bitline and the first latch block, and configured to transfer a second latch data to the second memory cell.

摘要翻译： 用于非易失性半导体存储器件的页面缓冲器包括被配置为将耦合到第一存储器单元的第一位线耦合到耦合到第二存储器单元的第二位线的开关，耦合到第一位线并被配置为传送的第一锁存块 向第一存储器单元提供第一锁存数据，以及耦合到第二位线和第一锁存块的第二锁存块，并且被配置为将第二锁存数据传送到第二存储器单元。

公开(公告)号：US07821825B2

公开(公告)日：2010-10-26

申请号：US12358009

申请日：2009-01-22

申请人： Ki-Tae Park ,  Jung-Dal Choi

发明人： Ki-Tae Park ,  Jung-Dal Choi

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A method of programming a flash memory includes applying a shielding voltage to at least one shielding line, which is interposed between a plurality of wordlines and a selection line and operable to reduce capacitance-coupling between the wordline and the selection line during the programming operation, and applying a program voltage to memory cells through one of the wordlines.

摘要翻译： 一种对闪速存储器进行编程的方法包括：对至少一个屏蔽线施加屏蔽电压，该屏蔽线介于多个字线和选择线之间，并且可操作以在编程操作期间减小字线和选择线之间的电容耦合， 以及通过字线之一向存储器单元施加编程电压。

公开(公告)号：US07812390B2

公开(公告)日：2010-10-12

申请号：US11777293

申请日：2007-07-13

申请人： Ki-Tae Park ,  Jung-Dal Choi ,  Jae-Sung Sim

发明人： Ki-Tae Park ,  Jung-Dal Choi ,  Jae-Sung Sim

IPC分类号： H01L25/065 ,  H01L27/115

CPC分类号： H01L27/11551 ,  G11C11/5621 ,  G11C16/0483 ,  G11C2211/5641 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor memory device includes a first substrate having at least one string including a first select transistor, a second select transistor, and first memory cells connected in series between the first and second select transistors of the first substrate. The semiconductor memory device further includes a second substrate having at least one string including a first select transistor, a second select transistor, and second memory cells connected in series between the first and second select transistors of the second substrate. The number of the first memory cells of the at least one string of the first substrate is different from a number of the second memory cells of the at least one string of the second substrate. For example, the number of second memory cells may be less than the number of first memory cells.

摘要翻译： 半导体存储器件包括具有包括第一选择晶体管，第二选择晶体管和串联连接在第一衬底的第一和第二选择晶体管之间的第一存储单元的至少一个串的第一衬底。 半导体存储器件还包括具有至少一个串的第二衬底，该至少一个串包括串联连接在第二衬底的第一和第二选择晶体管之间的第一选择晶体管，第二选择晶体管和第二存储单元。 第一衬底的至少一个串的第一存储器单元的数量与第二衬底的至少一个串的第二存储单元的数量不同。 例如，第二存储器单元的数量可以小于第一存储器单元的数量。

公开(公告)号：US07776687B2

公开(公告)日：2010-08-17

申请号：US11797401

申请日：2007-05-03

申请人： Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jung-Dal Choi ,  Jong-Sun Sel ,  Ju-Hyung Kim ,  Sang-Hun Jeon

发明人： Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jung-Dal Choi ,  Jong-Sun Sel ,  Ju-Hyung Kim ,  Sang-Hun Jeon

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/823462 ,  H01L21/823475 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/7883

摘要： A semiconductor device has a gate contact structure, including a semiconductor substrate, a polycrystalline silicon layer used as a gate electrode of a transistor, a middle conductive layer, a top metal layer having an opening exposing the polycrystalline silicon layer, and a contact plug directly contacting the polycrystalline silicon layer through the opening.

摘要翻译： 半导体器件具有栅极接触结构，包括半导体衬底，用作晶体管的栅电极的多晶硅层，中间导电层，具有暴露多晶硅层的开口的顶部金属层和直接接触的接触插塞 使多晶硅层通过开口接触。

公开(公告)号：US07773422B2

公开(公告)日：2010-08-10

申请号：US12052666

申请日：2008-03-20

申请人： Ki-Tae Park ,  Jung-Dal Choi ,  Sung-Kyu Jo

发明人： Ki-Tae Park ,  Jung-Dal Choi ,  Sung-Kyu Jo

IPC分类号： G11C11/04

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/24

摘要： A page buffer for a non-volatile semiconductor memory device includes a switch configured to couple a first bitline coupled to a first memory cell to a second bitline coupled to a second memory cell, a first latch block coupled to the first bitline and configured to transfer a first latch data to the first memory cell, and a second latch block coupled to the second bitline and the first latch block, and configured to transfer a second latch data to the second memory cell.

摘要翻译： 用于非易失性半导体存储器件的页面缓冲器包括被配置为将耦合到第一存储器单元的第一位线耦合到耦合到第二存储器单元的第二位线的开关，耦合到第一位线并被配置为传送的第一锁存块 向第一存储器单元提供第一锁存数据，以及耦合到第二位线和第一锁存块的第二锁存块，并且被配置为将第二锁存数据传送到第二存储器单元。

公开(公告)号：US07772639B2

公开(公告)日：2010-08-10

申请号：US11700315

申请日：2007-01-31

申请人： Chang-Seok Kang ,  Jung-Dal Choi ,  Ju-Hyung Kim ,  Jong-Sun Sel ,  Jae-Sung Sim ,  Sang-Hun Jeon

发明人： Chang-Seok Kang ,  Jung-Dal Choi ,  Ju-Hyung Kim ,  Jong-Sun Sel ,  Jae-Sung Sim ,  Sang-Hun Jeon

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： Nonvolatile memory devices including device isolation patterns on a semiconductor substrate are provided. The device isolation patterns define a cell active region and a peripheral active region of the semiconductor substrate. Cell gate electrodes are provided that cross over the cell active regions. Memory cell patterns are provided between the cell gate electrodes and the cell active regions and extend toward the device isolation patterns. A tunnel insulation film is provided between the memory cell pattern and the cell active region. Related methods of fabricating nonvolatile memory devices are also provided herein.

摘要翻译： 提供包括半导体衬底上的器件隔离图案的非易失性存储器件。 器件隔离图案限定半导体衬底的单元有源区和外围有源区。 提供跨越电池有源区的电池栅电极。 在单元栅极电极和单元有源区之间提供存储单元图案，并朝向器件隔离图案延伸。 在存储单元图形和单元有源区之间设置隧道绝缘膜。 本文还提供了制造非易失性存储器件的相关方法。

公开(公告)号：US07759723B2

公开(公告)日：2010-07-20

申请号：US12133858

申请日：2008-06-05

申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Byoung-Woo Ye

发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Byoung-Woo Ye

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/513 ,  H01L29/7881 ,  H01L29/792

摘要： A non-volatile memory device includes a tunneling insulating layer on a semiconductor substrate, a charge storage layer, a blocking insulating layer, and a gate electrode. The charge storage layer is on the tunnel insulating layer and has a smaller band gap than the tunnel insulating layer and has a greater band gap than the semiconductor substrate. The blocking insulating layer is on the charge storage layer and has a greater band gap than the charge storage layer and has a smaller band gap than the tunnel insulating layer. The gate electrode is on the blocking insulating layer.

公开(公告)号：US20090135647A1

公开(公告)日：2009-05-28

申请号：US12358009

申请日：2009-01-22

申请人： Ki-Tae Park ,  Jung-Dal Choi

发明人： Ki-Tae Park ,  Jung-Dal Choi

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A method of programming a flash memory includes applying a shielding voltage to at least one shielding line, which is interposed between a plurality of wordlines and a selection line and operable to reduce capacitance-coupling between the wordline and the selection line during the programming operation, and applying a program voltage to memory cells through one of the wordlines.

摘要翻译： 一种对闪速存储器进行编程的方法包括：对至少一个屏蔽线施加屏蔽电压，该屏蔽线介于多个字线和选择线之间，并且可操作以在编程操作期间减小字线和选择线之间的电容耦合， 以及通过字线之一向存储器单元施加编程电压。

公开(公告)号：US20090097326A1

公开(公告)日：2009-04-16

申请号：US12340250

申请日：2008-12-19

申请人： Ki-Tae Park ,  Jung-Dal Choi ,  Jong-Sun Sel ,  Yoo-Cheol Shin

发明人： Ki-Tae Park ,  Jung-Dal Choi ,  Jong-Sun Sel ,  Yoo-Cheol Shin

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/107 ,  G11C16/12 ,  G11C16/3445

摘要： A NAND flash memory device includes a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of a plurality of serially-connected memory cells, a second word line voltage greater than the first word line voltage to a selected one of the plurality of memory cells, and a third word line voltage lower than the first word line voltage to a dummy memory cell connected in series with the plurality of memory cells. In other embodiments, a control circuit is configured to program a dummy memory cell before and/or after each erase operation on a plurality of memory cells connected in series therewith. In still other embodiments, a control circuit is configured to forego erasure of a dummy memory cell while erasing a plurality of memory cells connected in series therewith.

摘要翻译： NAND闪速存储器件包括控制电路，其被配置为在编程操作期间将第一字线电压施加到多个串联存储器单元中的未选择的电压，第二字线电压大于第一字线电压 到多个存储单元中的一个选择的一个，以及比第一字线电压低的第三字线电压到与多个存储单元串联连接的虚拟存储单元。 在其他实施例中，控制电路被配置为在与每个擦除操作之间的每个擦除操作之前和/或之后对与其串联的多个存储器单元进行编程。 在其他实施例中，控制电路被配置为在擦除与其串联连接的多个存储器单元时，放弃擦除伪存储器单元。

公开(公告)号：US20080237700A1

公开(公告)日：2008-10-02

申请号：US12078143

申请日：2008-03-27

申请人： Ju-Hyung Kim ,  Jung-Dal Choi ,  Jang-Hyun You

发明人： Ju-Hyung Kim ,  Jung-Dal Choi ,  Jang-Hyun You

IPC分类号： H01L27/115 ,  H01L21/8247

CPC分类号： H01L21/28282 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/11573

摘要： A nonvolatile memory device and method of making the same are provided. Memory cells may be provided in a cell area wherein each memory cell has an insulative structure including a tunnel insulating layer, a floating trap layer and a blocking layer, and a conductive structure including an energy barrier layer, a barrier metal layer and a low resistance gate electrode. A material having a lower resistivity may be used as the gate electrode so as to avoid problems associated with increased resistance and to allow the gate electrode to be made relatively thin. The memory device may further include transistors in the peripheral area, which may have a gate dielectric layer, a lower gate electrode of poly-silicon and an upper gate electrode made of metal silicide, allowing an improved interface with the lower gate electrode without diffusion or reaction while providing a lower resistance.

摘要翻译： 提供了一种非易失性存储器件及其制造方法。 存储单元可以设置在单元区域中，其中每个存储单元具有包括隧道绝缘层，浮动陷阱层和阻挡层的绝缘结构，以及包括能量阻挡层，阻挡金属层和低电阻的导电结构 栅电极。 可以使用具有较低电阻率的材料作为栅电极，以避免与电阻增加相关的问题，并允许栅电极相对较薄。 存储器件还可以包括在外围区域中的晶体管，其可以具有栅极电介质层，多晶硅的下部栅电极和由金属硅化物制成的上部栅电极，从而允许与下部栅电极的改善的界面而不扩散或 同时提供较低的电阻。