中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

102 records (took 0.025 seconds)

    Multi-level run-length limited finite state machine with multi-penalty
    73.
    发明授权
    Multi-level run-length limited finite state machine with multi-penalty 有权
    多级游程限制有限状态机多罚

    公开(公告)号：US08792195B2

    公开(公告)日：2014-07-29

    申请号：US13654931

    申请日：2012-10-18

    Applicant: LSI Corporation

    Inventor： Wu Chang ,  Razmik Karabed ,  Fan Zhang

    IPC: G11B5/00 ,  G11B20/18 ,  G11B20/24

    CPC classification number: G11B20/1833 ,  G11B20/10277 ,  G11B20/10287

    Abstract: Techniques are described for constructing maximum transition run (MTR) modulation code based upon a multi-level (ML) run-length limited (RLL) finite state machine (FSM) that implements different sets of penalties. A processor is configured to receive information from a hard disk drive (HDD) via a read channel and recover data from the HDD using MTR modulation code. A memory has computer executable instructions configured for execution by the processor to model a magnetic recording channel as a partial response channel, model a source of information to the magnetic recording channel to provide an optimized Markov source, and construct an MTR modulation code to mimic the optimized Markov source based upon an FSM having a limited transition run length and a multi-level periodic structure. The FSM provides at least two different sets of penalties in a period.

    Abstract translation: 描述了基于实现不同处罚集的多级（ML）游程限制（RLL）有限状态机（FSM）来构建最大过渡运行（MTR）调制码的技术。 处理器被配置为经由读通道从硬盘驱动器（HDD）接收信息，并且使用MTR调制码从HDD恢复数据。 存储器具有被配置为由处理器执行以将磁记录通道建模为部分响应通道的计算机可执行指令，将信息源建模到磁记录通道以提供优化的马尔可夫源，并构建MTR调制码以模拟 基于具有有限转换行程长度和多级周期结构的FSM的优化马尔可夫源。 FSM在一段时间内至少提供两套不同的罚则。

    Signal processing circuitry with frontend and backend circuitry controlled by separate clocks
    74.
    发明授权
    Signal processing circuitry with frontend and backend circuitry controlled by separate clocks 有权
    信号处理电路，前端和后端电路由单独的时钟控制

    公开(公告)号：US08773799B1

    公开(公告)日：2014-07-08

    申请号：US13724946

    申请日：2012-12-21

    Applicant: LSI Corporation

    Inventor： Suharli Tedja ,  Shaohua Yang ,  Fan Zhang ,  Qi Zuo ,  Joseph Garofalo ,  Yu Kou

    IPC: G11B5/09

    CPC classification number: G06F1/06 ,  G06F1/08 ,  G06F1/206

    Abstract: An apparatus comprises read channel circuitry and associated signal processing circuitry comprising frontend processing circuitry and backend processing circuitry. The frontend processing circuitry comprises a loop detector and equalizer configured to determine an equalized read channel signal from a read channel signal and a decoding module configured to apply verification and scrambling processing on a decoded read channel signal. The backend processing circuitry comprises a backend detector, an interleaver, a backend decoder, and a de-interleaver configured to perform an iterative decoding process on the equalized read channel signal to determine the decoded read channel signal. The frontend processing circuitry is controlled by a first clock having an associated first clock rate and the backend processing circuitry is controlled by a selected one of the first clock and a second clock having an associated second clock rate determined at least in part by the first clock rate and a maximum clock rate.

    Abstract translation: 一种装置包括读通道电路和包括前端处理电路和后端处理电路的相关信号处理电路。 前端处理电路包括环路检测器和均衡器，其被配置为从读取信道信号确定均衡的读取信道信号，以及解码模块，被配置为对解码的读取信道信号进行验证和加扰处理。 后端处理电路包括后端检测器，交织器，后端解码器和解交织器，被配置为对均衡的读信道信号执行迭代解码处理，以确定解码的读信道信号。 前端处理电路由具有相关联的第一时钟速率的第一时钟控制，并且后端处理电路由第一时钟中所选择的一个控制，第二时钟具有至少部分地由第一时钟确定的相关联的第二时钟速率 速率和最大时钟速率。

    Low Density Parity Check Decoder With Dynamic Scaling
    75.
    发明申请
    Low Density Parity Check Decoder With Dynamic Scaling 有权
    低密度奇偶校验解码器与动态缩放

    公开(公告)号：US20140173385A1

    公开(公告)日：2014-06-19

    申请号：US13777841

    申请日：2013-02-26

    Applicant: LSI CORPORATION

    Inventor： Shu Li ,  Zongwang Li ,  Shaohua Yang ,  Chung-Li Wang ,  Fan Zhang

    IPC: H03M13/13 ,  G11B20/18

    CPC classification number: H03M13/1117 ,  G11B20/1833 ,  G11B2020/185 ,  H03M13/1111 ,  H03M13/1171 ,  H03M13/27 ,  H03M13/6331 ,  H03M13/658

    Abstract: A data processing system is disclosed including a low density parity check decoder with a variable node processor, a check node processor and a scaler circuit. The low density parity check decoder is operable to scale soft information with a scaling factor in the scaler circuit while iteratively generating and processing check node to variable node messages in the variable node processor and variable node to check node messages in the check node processor between a plurality of check nodes and variable nodes. The scaling factor is derived from a distribution of possible values in an input to the low density parity check decoder.

    Abstract translation: 公开了一种数据处理系统，包括具有可变节点处理器的低密度奇偶校验解码器，校验节点处理器和缩放器电路。 低密度奇偶校验解码器可用于在缩放器电路中缩放具有缩放因子的软信息，同时在可变节点处理器和变量节点中对可变节点消息进行迭代生成并处理校验节点，以校验校验节点处理器中的节点消息 多个检查节点和可变节点。 缩放因子是从低密度奇偶校验解码器的输入中的可能值的分布导出的。

    MULTI-LEVEL RUN-LENGTH LIMITED FINITE STATE MACHINE FOR MAGNETIC RECORDING CHANNEL
    77.
    发明申请
    MULTI-LEVEL RUN-LENGTH LIMITED FINITE STATE MACHINE FOR MAGNETIC RECORDING CHANNEL 有权
    多级运行有限公司有限公司磁记录通道有限公司

    公开(公告)号：US20140111880A1

    公开(公告)日：2014-04-24

    申请号：US13654893

    申请日：2012-10-18

    Applicant: LSI CORPORATION

    Inventor： Wu Chang ,  Razmik Karabed ,  Shaohua Yang ,  Fan Zhang

    IPC: G11B5/02

    CPC classification number: G11B5/02 ,  G06F11/16 ,  G11B20/10277

    Abstract: A system is described for constructing maximum transition run modulation code based upon a multi-level run-length limited finite state machine. A processor is configured to receive information from a hard disk drive via a read channel and recover data from the hard disk drive using maximum transition run modulation code. A memory has computer executable instructions configured for execution by the processor to model a magnetic recording channel as a partial response channel, model a source of information to the magnetic recording channel to provide an optimized Markov source, and construct a maximum transition run modulation code to mimic the optimized Markov source based upon a finite state machine having a limited transition run length and a multi-level periodic structure.

    Abstract translation: 描述了一种基于多级游程限制有限状态机来构建最大过渡运行调制码的系统。 处理器被配置为经由读取通道从硬盘驱动器接收信息，并使用最大过渡运行调制码从硬盘驱动器恢复数据。 存储器具有被配置为由处理器执行以将磁记录通道建模为部分响应通道的计算机可执行指令，将信息源建模到磁记录通道以提供优化马尔可夫源，并且构建最大过渡运行调制码 基于具有有限转换行程长度和多级周期性结构的有限状态机模拟优化的马尔可夫源。

    Pattern-dependent LLR manipulation
    78.
    发明授权
    Pattern-dependent LLR manipulation 有权
    模式相关的LLR操作

    公开(公告)号：US08649118B1

    公开(公告)日：2014-02-11

    申请号：US13626030

    申请日：2012-09-25

    Applicant: LSI Corporation

    Inventor： Wu Chang ,  Fan Zhang ,  Jun Xiao

    IPC: G11B5/02

    CPC classification number: H03M13/612 ,  G11B20/1833

    Abstract: Methods are provided for pattern-dependent log likelihood ratio (LLR) manipulation of a hard disk drive detector output. Generally, by observing a pattern dependency of LLRs, various rules for LLR manipulation at the detector output are outlined. The rules may provide more reliable LLR values, such as by improving signal-to-noise ratio (SNR) of the hard disk drive detector output.

    Abstract translation: 提供了用于硬盘驱动器检测器输出的模式相关对数似然比（LLR）操纵的方法。 通常，通过观察LLR的模式依赖性，概述了检测器输出处的LLR操作的各种规则。 规则可以提供更可靠的LLR值，例如通过提高硬盘驱动器检测器输出的信噪比（SNR）。

    Systems and methods for lost synchronization data set reprocessing
    80.
    发明授权
    Systems and methods for lost synchronization data set reprocessing 有权
    丢失同步数据集再处理的系统和方法

    公开(公告)号：US09323625B2

    公开(公告)日：2016-04-26

    申请号：US14080935

    申请日：2013-11-15

    Applicant: LSI Corporation

    Inventor： Shu Li ,  Fan Zhang ,  Jun Xiao ,  Jefferson Singleton

    IPC: H04L7/04 ,  G06F11/14 ,  G11B5/09 ,  G11B20/12 ,  G06F17/30

    CPC classification number: G06F11/1469 ,  G06F17/30424 ,  G06F17/30581 ,  G11B5/09 ,  G11B20/1217 ,  G11B2020/1287

    Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for segmenting a data set and recovering the segmented data set. In one particular example, a method is disclosed that includes: querying an input data set for an actual sync mark; forcing a proxy sync mark where the actual sync mark is not found in the input data set; applying data processing to the input data set to yield a processed output; correlating a potion of the processed output with a corresponding portion of the input data set to yield a true sync location; calculating a difference between the true sync location and the location of the forced sync mark to yield an offset; re-forcing the proxy sync mark based upon the offset; and re-applying the data processing to the input data set aligned using the re-forced proxy sync mark to yield a re-processed output.

    Abstract translation: 一般涉及数据处理的系统和方法，更具体地涉及用于分割数据集并恢复分段数据集的系统和方法。 在一个具体示例中，公开了一种方法，其包括：查询实际同步标记的输入数据集; 强制代理同步标记，其中在输入数据集中没有找到实际的同步标记; 将数据处理应用于输入数据集以产生经处理的输出; 将处理的输出的一部分与输入数据集的相应部分相关联以产生真正的同步位置; 计算真实同步位置和强制同步标记的位置之间的差异以产生偏移; 基于偏移重新强制代理同步标记; 并且将数据处理重新应用于使用重新强制代理同步标记对齐的输入数据集，以产生重新处理的输出。

Patent Agency Ranking