公开(公告)号：US20220214837A1

公开(公告)日：2022-07-07

申请号：US17706157

申请日：2022-03-28

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Bruce A. Liikanen

IPC: G06F3/06 ,  G11C16/26 ,  G11C16/34

Abstract: The present disclosure is directed to read sample offset most probable bit operation associated with a memory component. A processing device generates a first set of read data associated with a memory component, the first set of read data comprising a first sequence of bit values. The processing device generates a second set of read data associated with the memory component, the second set of read data comprising a second sequence of bit values. The processing device generates a third set of read data associated with the memory component, the third set of read data comprising a third sequence of bit values. A most probable bit operation is performed to compare the first sequence of bit values, the second sequence of bit values, and the third sequence of bit values to generate and store a most probable bit sequence.

公开(公告)号：US20220199187A1

公开(公告)日：2022-06-23

申请号：US17125895

申请日：2020-12-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vamsi Pavan Rayaprolu ,  Shane Nowell ,  Michael Sheperek ,  Steven Michael Kientz

IPC: G11C29/44 ,  G11C29/42 ,  G11C29/10 ,  G11C29/12

Abstract: A system can include a memory device and a processing device to perform operations that include performing a block family calibration scan of the memory device, wherein the calibration scan comprises a plurality of scan iterations, wherein each scan iteration is initiated in accordance with at least one threshold scan criterion, and wherein each scan iteration comprises identifying at least one first voltage bin, wherein each first voltage bin is associated with a plurality of read level offsets, identifying, according to a block family creation order, an oldest block family from a plurality of block families associated with the first voltage bin, and updating at least one bin pointer of the oldest block family based on a data state metric of at least one block of the oldest block family.

公开(公告)号：US20220155955A1

公开(公告)日：2022-05-19

申请号：US17098861

申请日：2020-11-16

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Kishore Kumar Muchherla ,  Shane Nowell

IPC: G06F3/06

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to create a first block family comprising a first set of blocks that have been programmed within at least one of a first specified time window or a first specified temperature window, wherein each block associated with the first block family is associated with a first set of read level offsets; create, a second block family comprising a second set of blocks that have been programmed within at least one of a second specified time window following the first specified time window or a second specified temperature window, wherein each block associated with the second block family is associated with a second set of read level offsets; and responsive to a determining that a threshold criterion is satisfied, combine the first and second block family.

公开(公告)号：US20220139460A1

公开(公告)日：2022-05-05

申请号：US17086964

申请日：2020-11-02

Applicant: Micron Technology, Inc.

Inventor： Bruce A. Liikanen ,  Michael Sheperek ,  Larry J. Koudele

IPC: G11C16/10 ,  G11C16/26 ,  G06F3/06

Abstract: A processing device establishes a first data group of memory cells of a memory sub-system and a second data group of memory cells of the memory sub-system. A first portion of the first data group is programmed at a threshold voltage level to set a first embedded data value. A second portion of the second data group of memory cells is programmed at the threshold voltage level offset by an offset voltage level to set a second embedded data value.

公开(公告)号：US20220137814A1

公开(公告)日：2022-05-05

申请号：US17084540

申请日：2020-10-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shane Nowell ,  Michael Sheperek ,  Larry J. Koudele ,  Bruce A. Liikanen ,  Steve Kientz

IPC: G06F3/06

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to open a first block family associated with the memory device; assign a first cursor of a plurality of cursors of the memory device to the first block family; responsive to programming a first block associated with the first cursor, associate the first block with the first block family; open, while the first block family is open, a second block family associated with the memory device; assign a second cursor of the plurality of cursors of the memory device to the second block family; and responsive to programming a second block associated with the second cursor, associate the second block with the second block family.

公开(公告)号：US20220059179A1

公开(公告)日：2022-02-24

申请号：US17301350

申请日：2021-03-31

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Bruce A. Liikanen ,  Steven Michael Kientz

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/12 ,  G11C16/16 ,  G11C16/26

Abstract: Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, responsive to detecting a triggering event, selecting a family of memory blocks of the memory device, the selected family being associated with a set of bins, each bin associated with a plurality of read voltage offsets to be applied to base read voltages during read operations. The operations performed by the processing device further include calibration operations to determine data state metric values characterizing application of read voltage offsets of various bins. The operations performed by the processing device further include identifying, based on the determined data state metrics, a target bin and associating the selected family with the target bin.

公开(公告)号：US20220057935A1

公开(公告)日：2022-02-24

申请号：US16947820

申请日：2020-08-19

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Larry J. Koudele ,  Bruce A. Liikanen ,  Steven Michael Kientz

IPC: G06F3/06 ,  G01K3/00 ,  G01K3/04 ,  G01K1/02 ,  G01K7/02

Abstract: A system comprising a memory device and a processing device, operatively coupled to the memory device. The processing device is to perform operations including initializing a block family associated with the memory device and measuring an opening temperature of the memory device at initialization of the block family. Responsive to programming a page residing on the memory device, the operations further include associating the page with the block family. The operations further include determining a temperature metric value by integrating, over time, an absolute temperature difference between the opening temperature and an immediate temperature of the memory device. The operations further include closing the block family in response to the temperature metric value being greater than or equal to a specified threshold temperature value.

公开(公告)号：US11177006B2

公开(公告)日：2021-11-16

申请号：US16775099

申请日：2020-01-28

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Larry J. Koudele ,  Steve Kientz

IPC: G06F3/06 ,  G11C16/26 ,  G11C11/56 ,  G11C16/04

Abstract: A system comprises a memory device comprising a plurality of memory cells; and a processing device coupled to the memory device, the processing device configured to iteratively: calibrate read levels based on associated read results, wherein the read levels are tracked via optimization target data that at least initially includes at least one read level in addition to a target trim; and remove a calibrated read level from the optimization target data when the calibrated read level satisfies a calibration condition.

公开(公告)号：US11120879B2

公开(公告)日：2021-09-14

申请号：US16534097

申请日：2019-08-07

Applicant: Micron Technology, Inc.

Inventor： Bruce A. Liikanen ,  Michael Sheperek ,  Larry J. Koudele

IPC: G11C16/14 ,  G11C16/34 ,  G06F3/06 ,  G11C16/04

Abstract: A processing device determines a set of difference error counts corresponding to multiple programming distributions of a memory sub-system. A valley having a lowest valley margin is identified based on a comparison of the set of difference error counts. Based on the set of difference error counts, a program targeting rule from a set of rules. A program targeting operation is performed, based on the program targeting rule, a program targeting operation to adjust a voltage associated with an erase distribution of the memory sub-system.

公开(公告)号：US11061752B2

公开(公告)日：2021-07-13

申请号：US16514644

申请日：2019-07-17

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Larry J. Koudele ,  Bruce A. Liikanen

IPC: G06F11/00 ,  G06F11/07 ,  G11C16/08 ,  G11C16/28 ,  G11C16/10

Abstract: Center error counts are determined for logical page types of the memory component. A first center error count is indicative of a number of bit errors for a first logical page type. A second center error count is indicative of a number of bit errors for a second logical page type. A modified page margin is determined based on a current page margin corresponding to the first logical page type. The current page margin corresponds to the first logical page type and is indicative of a ratio of the first center error count to the second center error count. The modified page margin is indicative of a modified ratio of a modified first center error count to the second center error count. The current page margin is adjusted corresponding to the first logical page type in accordance with the modified page margin.