公开(公告)号：US20230214148A1

公开(公告)日：2023-07-06

申请号：US17652229

申请日：2022-02-23

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Kenneth M. Curewitz ,  Helena Caminal ,  Ameen D. Akel

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods, systems, and devices for redundant computing across planes are described. A device may perform a computational operation on first data that is stored in a first plane that includes content-addressable memory cells. The first data may be representative of a set of contiguous bits of a vector. The device may perform, concurrent with performing the computational operation on the first data, the computational operation on second data that is stored in a second plane. The second data may be representative of the set of contiguous bits of the vector. The device may read from the first plane and write to the second plane, third data representative of a result of the computational operation on the first data.

公开(公告)号：US11693657B2

公开(公告)日：2023-07-04

申请号：US16717890

申请日：2019-12-17

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Sean S. Eilert ,  Sivagnanam Parthasarathy ,  Shivasankar Gunasekaran ,  Ameen D. Akel

IPC: G06F9/38 ,  G11C7/06 ,  G06F9/30 ,  G11C7/10 ,  G11C8/10

CPC classification number: G06F9/3001 ,  G06F9/3893 ,  G11C7/06 ,  G11C7/1096 ,  G11C8/10

Abstract: Methods, apparatuses, and systems for in- or near-memory processing are described. Strings of bits (e.g., vectors) may be fetched and processed in logic of a memory device without involving a separate processing unit. Operations (e.g., arithmetic operations) may be performed on numbers stored in a bit-serial way during a single sequence of clock cycles. Arithmetic may thus be performed in a single pass as numbers are bits of two or more strings of bits are fetched and without intermediate storage of the numbers. Vectors may be fetched (e.g., identified, transmitted, received) from one or more bit lines. Registers of the memory array may be used to write (e.g., store or temporarily store) results or ancillary bits (e.g., carry bits or carry flags) that facilitate arithmetic operations. Circuitry near, adjacent, or under the memory array may employ XOR or AND (or other) logic to fetch, organize, or operate on the data.

公开(公告)号：US20230051480A1

公开(公告)日：2023-02-16

申请号：US17885374

申请日：2022-08-10

Applicant: Micron Technology, Inc.

Inventor： Aliasger T. Zaidy ,  Glen E. Hush ,  Sean S. Eilert ,  Kunal R. Parekh

IPC: G11C11/4093 ,  G11C11/4096 ,  G06F3/06 ,  G06F13/16

Abstract: A memory device includes a memory die bonded to a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and memory die. The logic die can also receive signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond. The logic die can perform a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data. The inputs and the outputs to the VV units can be configured based on a mode of the logic die.

公开(公告)号：US20230049683A1

公开(公告)日：2023-02-16

申请号：US17884775

申请日：2022-08-10

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Sean S. Eilert ,  Aliasger T. Zaidy ,  Glen E. Hush

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L21/78 ,  H01L25/00

Abstract: Methods, systems, and devices related to forming a wafer-on-wafer bond between a memory die and a logic die. A plurality of first metal pads can be formed on a first wafer and a plurality of second metal pads can be formed on a second wafer. A subset of the first metal pads can be bonded to a subset of the second metal pads via a wafer-on-wafer bonding process. Each of a plurality of memory devices on the first wafer can be aligned with and coupled to at least a respective one of a plurality of logic devices on the second wafer. The bonded first and second wafers can be singulated into individual wafer-on-wafer bonded memory and logic dies.

公开(公告)号：US20230048628A1

公开(公告)日：2023-02-16

申请号：US17885269

申请日：2022-08-10

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Glen E. Hush ,  Sean S. Eilert ,  Aliasger T. Zaidy

IPC: H01L23/00 ,  H01L25/065

Abstract: A wafer-on-wafer bonded memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. A memory device formed on a memory die can include many global input/output lines and many arrays of memory cells. Each array of memory cells can include respective local input/output (LIO) lines coupled to a global input/output line. A logic device can be formed on a logic die. A bond, formed between the memory die and the logic die via a wafer-on-wafer bonding process, can couple the many global input/output lines to the logic device.

公开(公告)号：US20230048103A1

公开(公告)日：2023-02-16

申请号：US17884781

申请日：2022-08-10

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Sean S. Eilert ,  Aliasger T. Zaidy ,  Glen E. Hush

IPC: H01L23/00 ,  H01L25/065

Abstract: Methods, systems, and devices related to a memory die and a logic die having a wafer-on-wafer bond therebetween. A memory die can include a memory array and a plurality of input/output (IO) lines coupled thereto. A logic die can include to a deep learning accelerator (DLA). The memory die can be coupled to the logic die by a wafer-on-wafer bond. The wafer-on-wafer bond can couple the plurality of IO lines to the DLA.

公开(公告)号：US20230009642A1

公开(公告)日：2023-01-12

申请号：US17369869

申请日：2021-07-07

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Justin Eno ,  Ameen D. Akel

IPC: G06F3/06 ,  H03M13/09 ,  H03M13/11

Abstract: Methods, systems, and devices for programmable metadata and related operations are described. A method may include receiving signaling that indicates a set of rules for transitions of states of metadata at a memory device storing the metadata. The memory device may receive a command from a host device associated with a set of data after receiving the set of rules. The memory device may transition metadata associated with the set of data stored at the memory device from a first state to a second state based in part on the set of rules and the command. The memory device may execute the command received from the host device.

公开(公告)号：US20220382609A1

公开(公告)日：2022-12-01

申请号：US17886253

申请日：2022-08-11

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Sean S. Eilert

IPC: G06F11/07 ,  G06F11/10 ,  G11C15/04 ,  G11C5/06 ,  G11C11/409

Abstract: Methods, systems, and devices for error control for content-addressable memory (CAM) are described. A CAM may store bit vectors as a set of subvectors, which each subvector stored in an independent aspect of the CAM, such as in a separate column or array of memory cells within the CAM. The CAM may similarly segment a queried input bit vector and identify, for each resulting input subvector, whether a matching subvector is stored by the CAM. The CAM may identify a match for the input bit vector when the number of matching subvectors satisfies a threshold. The CAM may validate a match based on comparing a stored bit vector corresponding to the identified match to the input bit vector. The stored bit vector may undergo error correction and may be stored in the CAM or another memory array, such as a dynamic random access memory (DRAM) array.

公开(公告)号：US11385961B2

公开(公告)日：2022-07-12

申请号：US16993959

申请日：2020-08-14

Applicant: Micron Technology, Inc.

Inventor： Justin Eno ,  William A. Melton ,  Sean S. Eilert

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/30 ,  G06F11/07

Abstract: Methods, systems, and devices for adaptive parity techniques for a memory device are described. An apparatus, such as a memory device, may use one or more error correction code (ECC) schemes, an error cache, or both to support access operations. The memory device may receive a command from a host device to read or write data. If the error cache includes an entry for the data, the memory device may read or write the data using a first ECC scheme. If the error cache does not include an entry for the data, the memory device may read or write the data without using an ECC scheme or using a second ECC scheme different than the first ECC scheme.

公开(公告)号：US11373695B2

公开(公告)日：2022-06-28

申请号：US16719907

申请日：2019-12-18

Applicant: Micron Technology, Inc.

Inventor： Shivam Swami ,  Sean S. Eilert ,  Ameen D. Akel

IPC: G11C11/22

Abstract: Methods, systems, and devices for memory accessing with auto-precharge are described. For example, a memory system may be configured to support an activate with auto-precharge command, which may be associated with a memory device opening a page of memory cells, latching respective logic states stored by the memory cells at a row buffer, writing logic states back to the page of memory cells, and maintaining the latched logic states at the row buffer (e.g., while maintaining power to latches of the row buffer, after closing the page of memory cells, while the page of memory cells is closed).