公开(公告)号：US20160079372A1

公开(公告)日：2016-03-17

申请号：US14942193

申请日：2015-11-16

Applicant: Jorge A. Kittl ,  Borna Josip Obradovic ,  Robert Christopher Bowen ,  Mark S. Rodder

Inventor： Jorge A. Kittl ,  Borna Josip Obradovic ,  Robert Christopher Bowen ,  Mark S. Rodder

IPC: H01L29/267 ,  H01L29/78

CPC classification number: H01L29/267 ,  H01L21/28575 ,  H01L29/0847 ,  H01L29/452 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device can include a channel region with a first semiconductor material for a majority carrier in the channel region during operation (on state) of the device and a metal contact. A source/drain region can include a semiconductor material alloy including a second semiconductor material and at least one heterojunction located between the metal contact and the channel region, wherein the heterojunction forms a band-edge offset for the majority carrier that is less than or equal to about 0.2 eV.

Abstract translation: 半导体器件可以包括具有第一半导体材料的沟道区域，用于在器件的操作（开状态）和金属接触处的沟道区域中的多数载流子。 源极/漏极区域可以包括半导体材料合金，其包括第二半导体材料和位于金属触点和沟道区域之间的至少一个异质结，其中异质结形成小于或等于多数载流子的带边偏移 至约0.2eV。

公开(公告)号：US20150035074A1

公开(公告)日：2015-02-05

申请号：US14227812

申请日：2014-03-27

Applicant: Borna J. Obradovic ,  Mark S. Rodder ,  Jorge A. Kittl ,  Robert C. Bowen ,  Ryan M. Hatcher

Inventor： Borna J. Obradovic ,  Mark S. Rodder ,  Jorge A. Kittl ,  Robert C. Bowen ,  Ryan M. Hatcher

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L29/785

Abstract: A finFET device can include a source/drain contact recess having an optimal depth beyond which an incremental decrease in a spreading resistance value for a horizontal portion of a source/drain contact in the recess provided by increased depth may be less than an incremental increase in total resistance due to the increase in the vertical portion of the source/drain contact at the increased depth.

Abstract translation: finFET器件可以包括具有最佳深度的源极/漏极接触凹部，超过该源极/漏极接触凹部，由增加的深度提供的凹部中的源极/漏极接触件的水平部分的扩展电阻值的增量减小可以小于 由于在增加的深度处源极/漏极接触件的垂直部分的增加导致的总电阻。

公开(公告)号：US20080185675A1

公开(公告)日：2008-08-07

申请号：US12101965

申请日：2008-04-12

Applicant: Rick L. Wise ,  Mark S. Rodder

Inventor： Rick L. Wise ,  Mark S. Rodder

IPC: H01L23/58

CPC classification number: H01L21/76224 ,  H01L21/823807 ,  H01L21/823878

Abstract: The present invention provides a trench isolation structure, a method of manufacture therefor and a method for manufacturing an integrated circuit including the same. The trench isolation structure (130), in one embodiment, includes a trench located within a substrate (110), the trench having a buffer layer (133) located on sidewalls thereof. The trench isolation structure (130) further includes a barrier layer (135) located over the buffer layer (133), and fill material (138) located over the barrier layer (135) and substantially filling the trench.

Abstract translation: 本发明提供一种沟槽隔离结构及其制造方法以及包括该沟槽隔离结构的集成电路的制造方法。 在一个实施例中，沟槽隔离结构（130）包括位于衬底（110）内的沟槽，沟槽具有位于其侧壁上的缓冲层（133）。 沟槽隔离结构（130）还包括位于缓冲层（133）上的阻挡层（135）和位于阻挡层（135）上方并且基本上填充沟槽的填充材料（138）。

公开(公告)号：US20070292240A1

公开(公告)日：2007-12-20

申请号：US11443333

申请日：2006-05-30

Applicant: Mark S. Rodder

Inventor： Mark S. Rodder

IPC: F16B15/02

CPC classification number: F16B15/02 ,  A47G1/168 ,  F16B11/006

Abstract: An anchor device for securing an object to a wall includes a body having first and second opposite facing surfaces, an adhesive material on the first surface, a pointed fastener extending outwardly from the second surface, and a protective cover positioned over a pointed end of the fastener. A center axis of the fastener may be laterally offset from a center axis of the body by an offset distance which is one-half to three quarters of a distance between the body center axis and a side edge of the body.

Abstract translation: 用于将物体固定到墙壁上的锚定装置包括：主体，其具有第一和第二相对的表面，第一表面上的粘合材料，从第二表面向外延伸的尖锐紧固件和位于 紧固件。 紧固件的中心轴线可以从身体的中心轴线横向偏移偏离距离，偏移距离是身体中心轴线和身体的侧边缘之间的距离的二分之一到四分之三。

公开(公告)号：US06583013B1

公开(公告)日：2003-06-24

申请号：US09452037

申请日：1999-11-30

Applicant: Mark S. Rodder ,  Jarvis B. Jacobs

Inventor： Mark S. Rodder ,  Jarvis B. Jacobs

IPC: H01L218236

CPC classification number: H01L21/823814 ,  H01L21/823857

Abstract: A mixed voltage circuit is formed by providing a substrate (12) having a first region (20) for forming a first device (106), a second region (22) for forming a second device (108) complementary to the first device (106), and a third region (24) for forming a third device (110) that operates at a different voltage than the first device (106). A gate layer (50) is formed outwardly of the first, second, and third regions (20, 22, 24). While maintaining a substantially uniform concentration of a dopant type (51) in the gate layer (50), a first gate electrode (56) is formed in the first region (20), a second gate electrode (58) is formed in the second region (22), and a third gate electrode (60) is formed in the third region (24). The third region (24) is protected while implanting dopants (72) into the first region (20) to form source and drain features (74) for the first device (106). The first region (20) is protected while implanting dopants (82) into the third region (24) to form disparate source and drain features (84) for the third device (110).

公开(公告)号：US06579770B2

公开(公告)日：2003-06-17

申请号：US09899783

申请日：2001-07-05

Applicant: Mark S. Rodder ,  Mahalingam Nandakumar

Inventor： Mark S. Rodder ,  Mahalingam Nandakumar

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/2652 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  Y10S438/926 ,  Y10S438/931

Abstract: A transistor (30) and method for forming a transistor using an edge blocking material (24) is disclosed herein. The edge blocking material (24) may be located adjacent a gate (22) or disposable gate or may be part of a disposable gate. During an angled pocket implant, the edge blocking material (24) blocks some dopant from entering the semiconductor body (10) and the dopant (18) placed under the edge blocking material is located at a given distance below the surface of the semiconductor body (10).

Abstract translation: 本文公开了一种用于使用边缘阻挡材料（24）形成晶体管的晶体管（30）和方法。 边缘阻挡材料（24）可以位于邻近门（22）或一次性门，或者可以是一次性门的一部分。 在成角度的袋式注入期间，边缘阻挡材料（24）阻挡一些掺杂剂进入半导体本体（10），并且位于边缘阻挡材料下面的掺杂剂（18）位于半导体本体表面下方给定的距离处 10）。

公开(公告)号：US06461928B2

公开(公告)日：2002-10-08

申请号：US09843559

申请日：2001-04-26

Applicant: Mark S. Rodder

Inventor： Mark S. Rodder

IPC: H01L21331

CPC classification number: H01L21/823412

Abstract: A method for fabricating an integrated circuit having analog and digital core devices. Using a first masking layer (118), a p-type type dopant is implanted to form drain extension regions (126, 122, 124) in the pMOS digital core region (102), pMOS I/O region (104), and the pMOS analog core region (106). Using a second masking layer (132), a n-type dopant is implanted into at least a drain side of the nMOS analog core region (110) and the nMOS I/O region (108) to for drain extension regions (142, 144) and into the pMOS digital core region (102). This forms a pocket region (140) in the pMOS digital core region (102) but not the pMOS analog core region (106) or the pMOS I/O region (104).

Abstract translation: 一种制造具有模拟和数字核心器件的集成电路的方法。 使用第一掩模层（118），注入p型掺杂剂以在pMOS数字核心区域（102），pMOS I / O区域（104）中形成漏极延伸区域（126,122,124），并且 pMOS模拟核心区域（106）。 使用第二掩模层（132），n型掺杂剂注入到nMOS模拟核心区域（110）和nMOS I / O区域（108）的至少漏极侧，以用于漏极延伸区域（142,144 ）并进入pMOS数字核心区域（102）。 这在pMOS数字核心区域（102）中形成口袋区域（140），而不是pMOS模拟核心区域（106）或pMOS I / O区域（104）。

公开(公告)号：US06326289B1

公开(公告)日：2001-12-04

申请号：US09378824

申请日：1999-08-23

Applicant: Mark S. Rodder ,  Jorge A. Kittl

Inventor： Mark S. Rodder ,  Jorge A. Kittl

IPC: H01L214763

CPC classification number: H01L29/66507 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/66575

Abstract: An embodiment of the instant invention is a method of making a transistor having a silicided gate structure insulatively disposed over a semiconductor substrate, the method comprising the steps of: forming the gate structure over the substrate (step 102 of FIG. 1); forming a source/drain regions and a channel region in the semiconductor substrate (step 108), the channel region situated between the source/drain regions and under the gate structure; forming a photoresist layer over the source/drain regions (step 110); amorphizing a portion of the gate structure by introducing an amorphizing substance into the gate structure (step 112); removing the photoresist layer after the step of amorphizing a portion of the gate structure step 114); forming a metal layer on the conductive structure, the metal layer interacts with the gate structure in the amorphized portion of the gate structure and the source/drain regions so as to form a lower resistivity silicide on the gate structure and the source/drain regions (step 116); and wherein the photoresist layer blocks the amorphizing substance from the source/drain regions and allows the amorphizing substance to enter the gate structure.

Abstract translation: 本发明的一个实施例是制造具有绝缘地设置在半导体衬底上的硅化栅结构的晶体管的方法，该方法包括以下步骤：在衬底上形成栅极结构（图1的步骤102）; 在半导体衬底中形成源极/漏极区域和沟道区域（步骤108），位于源极/漏极区域之间并位于栅极结构之下的沟道区域; 在源/漏区上形成光致抗蚀剂层（步骤110）; 通过将非晶化物质引入到栅极结构中来使栅极结构的一部分非晶化（步骤112）; 在门结构步骤114）的一部分非晶化步骤之后去除光致抗蚀剂层; 在导电结构上形成金属层，金属层与栅极结构和源极/漏极区域的非晶化部分中的栅极结构相互作用，以在栅极结构和源极/漏极区域上形成低电阻率硅化物（ 步骤116）; 并且其中所述光致抗蚀剂层从所述源极/漏极区域阻挡所述非晶化物质并且允许所述非晶化物质进入所述栅极结构。

公开(公告)号：US6124627A

公开(公告)日：2000-09-26

申请号：US334991

申请日：1999-06-17

Applicant: Mark S. Rodder ,  William U. Liu

Inventor： Mark S. Rodder ,  William U. Liu

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/423 ,  H01L29/78 ,  H01L29/40

CPC classification number: H01L29/66477 ,  H01L21/28114 ,  H01L29/165 ,  H01L29/267 ,  H01L29/42376 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/66537 ,  H01L29/66545

Abstract: A MOSFET (100) having a heterostructure raised source/drain region and method of making the same. A two layer raised source drain region (106) is located adjacent a gate structure (112). The first layer (106a) is a barrier layer comprising a first material (e.g., SiGe, SiC). The second layer (106b) comprises a second, different material (e.g. Si). The material of the barrier layer (106a) is chosen to provide an energy band barrier between the raised source/drain region (106) and the channel region (108).

Abstract translation: 具有异质结构的源极/漏极区域的MOSFET（100）及其制造方法。 两层凸起的源极漏极区（106）位于栅极结构（112）附近。 第一层（106a）是包含第一材料（例如SiGe，SiC）的阻挡层。 第二层（106b）包括第二不同材料（例如Si）。 选择阻挡层（106a）的材料以在凸起的源极/漏极区域（106）和沟道区域（108）之间提供能带屏障。

公开(公告)号：US6063677A

公开(公告)日：2000-05-16

申请号：US957503

申请日：1997-10-24

Applicant: Mark S. Rodder ,  Richard A. Chapman

Inventor： Mark S. Rodder ,  Richard A. Chapman

IPC: H01L29/786 ,  H01L21/225 ,  H01L21/336 ,  H01L21/4763

CPC classification number: H01L29/41783 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L21/2257

Abstract: A method for forming a MOSFET transistor (100) using a disposable gate (120). A disposable gate (120) having at least two materials (122,124) that may be etched selectively with respect to each other is formed on a semiconductor substrate (102). Source/drain regions (104) are then formed adjacent the disposable gate. The source/drain regions may, for example, include raised source/drain regions (106). An insulator layer (114) is then deposited over the structure and then a portion of the insulator layer (114) over the disposable gate (120) is removed (e.g., using CMP or an etch-back). The composition of the insulator layer (114) is chosen such that the top layer (124) of the disposable gate (120) may be removed selectively with respect to the insulator layer (114). The disposable gate (120) is then removed and a channel implant may be performed that is self-aligned and only in the channel region. The gate dielectric (110) and gate electrode (112) are then formed.

Abstract translation: 一种使用一次性栅极（120）形成MOSFET晶体管（100）的方法。 在半导体衬底（102）上形成具有可相对于彼此选择性蚀刻的至少两种材料（122,124）的一次性栅极（120）。 然后在一次性栅极附近形成源/漏区（104）。 源极/漏极区域可以例如包括升高的源极/漏极区域（106）。 然后将绝缘体层（114）沉积在结构上，然后去除一次性栅极（120）上的绝缘体层（114）的一部分（例如，使用CMP或回蚀刻）。 选择绝缘体层（114）的组成，使得一次性栅极（120）的顶层（124）可相对于绝缘体层（114）选择性地移除。 然后去除一次性门（120），并且可以执行仅在通道区域中自对准的通道注入。 然后形成栅极电介质（110）和栅电极（112）。