公开(公告)号：US07781286B2

公开(公告)日：2010-08-24

申请号：US11767661

申请日：2007-06-25

申请人： Masaaki Higashitani

发明人： Masaaki Higashitani

IPC分类号： H01L21/336

CPC分类号： H01L27/11524 ,  H01L23/552 ,  H01L27/0203 ,  H01L27/115 ,  H01L27/11521 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating non-volatile storage having individually controllable shield plates between storage elements. The shield plates are formed by depositing a conductive material such as doped polysilicon between storage elements and their associated word lines, and providing contacts for the shield plates. The shield plates reduce electromagnetic coupling between floating gates of the storage elements, and can be used to optimize programming, read and erase operations. In one approach, the shield plates provide a field induced conductivity between storage elements in a NAND string during a sense operation so that source/drain implants are not needed in the substrate. In some control schemes, alternating high and low voltages are applied to the shield plates. In other control schemes, a common voltage is applied to the shield plates.

摘要翻译： 一种用于制造在存储元件之间具有单独可控屏蔽板的非易失性存储器的方法。 屏蔽板通过在存储元件和它们相关联的字线之间沉积诸如掺杂多晶硅的导电材料并且为屏蔽板提供触点而形成。 屏蔽板减少存储元件的浮动栅极之间的电磁耦合，可用于优化编程，读取和擦除操作。 在一种方法中，屏蔽板在感测操作期间在NAND串中的存储元件之间提供场感应导电性，使得在衬底中不需要源极/漏极注入。 在一些控制方案中，交替的高电压和低电压被施加到屏蔽板。 在其他控制方案中，向屏蔽板施加公共电压。

公开(公告)号：US20100172187A1

公开(公告)日：2010-07-08

申请号：US12349417

申请日：2009-01-06

申请人： Mohan Vamsi Dunga ,  Man Mui ,  Masaaki Higashitani

发明人： Mohan Vamsi Dunga ,  Man Mui ,  Masaaki Higashitani

IPC分类号： G11C16/06 ,  G11C7/00 ,  G11C7/06

CPC分类号： G11C11/5642 ,  G11C16/26

摘要： A sense amplifier is disclosed. One embodiment is a sensing circuit that includes a sensing device and a sense transistor coupled to the sensing device. A first switch that is coupled to the sense transistor and to the sensing device causes the sensing device to be charged to a first voltage that is a function of the threshold voltage of the sense transistor. One or more second switches that are coupled to the sensing device and to a target element. The second switches couple the sensing device to the target element to modify the first voltage on the sensing device and decouple the target element from the sensing device during a sense phase in which the modified first voltage is applied to the sense transistor. A condition of the target element is determined based on whether or not the sense transistor turns on in response to applying the modified first voltage to the sense transistor.

摘要翻译： 公开了一种读出放大器。 一个实施例是感测电路，其包括耦合到感测装置的感测装置和感测晶体管。 耦合到感测晶体管和感测装置的第一开关使得感测装置被充电到作为感测晶体管的阈值电压的函数的第一电压。 耦合到感测装置和目标元件的一个或多个第二开关。 第二开关将感测装置耦合到目标元件以修改感测装置上的第一电压，并且在将修改的第一电压施加到感测晶体管的感测阶段期间将目标元件与感测装置分离。 目标元件的条件基于响应于将修改的第一电压施加到感测晶体管是否导通而确定。

公开(公告)号：US07737483B2

公开(公告)日：2010-06-15

申请号：US11296235

申请日：2005-12-06

申请人： Masaaki Higashitani

发明人： Masaaki Higashitani

IPC分类号： H01L29/76

CPC分类号： H01L27/11521 ,  H01L21/76877 ,  H01L27/115 ,  H01L27/11524

摘要： A plug is formed by depositing a first material to partially fill an opening, leaving an unfilled portion with a lower aspect ratio than the original opening. A second material is then deposited to fill the remaining portion of the opening. The first material has good filling characteristics but has higher resistivity than the second material. The second material has low resistivity to give the plug low resistance.

摘要翻译： 通过沉积第一材料以部分地填充开口形成插塞，留下具有比原始开口更低的纵横比的未填充部分。 然后沉积第二种材料以填充开口的剩余部分。 第一种材料具有良好的填充特性，但具有比第二种材料更高的电阻率。 第二种材料具有低电阻率，使插头具有低电阻。

公开(公告)号：US20100091569A1

公开(公告)日：2010-04-15

申请号：US12641113

申请日：2009-12-17

申请人： Masaaki Higashitani

发明人： Masaaki Higashitani

IPC分类号： G11C16/04

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11543

摘要： Word lines of a NAND flash memory array are formed by concentric, rectangular shaped, closed loops that have a width of approximately half the minimum feature size of the patterning process used. The resulting circuits have word lines linked together so that peripheral circuits are shared. Separate erase blocks are established by shield plates.

摘要翻译： NAND闪速存储器阵列的字线由同心的矩形形状的闭环形成，其具有大约是所使用的图案化工艺的最小特征尺寸的一半的宽度。 所得到的电路具有连接在一起的字线，使得外围电路被共享。 单独的擦除块由屏蔽板建立。

公开(公告)号：US07616490B2

公开(公告)日：2009-11-10

申请号：US11550383

申请日：2006-10-17

申请人： Nima Mokhlesi ,  Masaaki Higashitani

发明人： Nima Mokhlesi ,  Masaaki Higashitani

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/22

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3454 ,  G11C2211/5621 ,  H01L21/28114 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42376 ,  H01L29/66825 ,  H01L29/7881

摘要： A select gate structure for a non-volatile storage system includes a select gate and a coupling electrode which are independently drivable. The coupling electrode is adjacent to a word line in a NAND string and has a voltage applied which reduces gate induced drain lowering (GIDL) program disturb of an adjacent unselected non-volatile storage element. In particular, an elevated voltage can be applied to the coupling electrode when the adjacent word line is used for programming. A reduced voltage is applied when a non-adjacent word line is used for programming. The voltage can also be set based on other programming criterion. The select gate is provided by a first conductive region while the coupling electrode is provided by a second conductive region formed over, and isolated from, the first conductive region.

摘要翻译： 用于非易失性存储系统的选择栅极结构包括独立驱动的选择栅极和耦合电极。 耦合电极与NAND串中的字线相邻，并且具有施加的电压，其减小相邻未选择的非易失性存储元件的栅极引起的漏极降低（GIDL）编程干扰。 特别地，当相邻字线用于编程时，可以将高电压施加到耦合电极。 当使用非相邻字线进行编程时，施加降低的电压。 电压也可以根据其他编程标准设定。 选择栅极由第一导电区域提供，而耦合电极由形成在第一导电区域上并与之隔离的第二导电区域提供。

公开(公告)号：US07615448B2

公开(公告)日：2009-11-10

申请号：US11296022

申请日：2005-12-06

申请人： Masaaki Higashitani

发明人： Masaaki Higashitani

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L21/76877 ,  H01L27/11521 ,  H01L27/11524

摘要： A plug is formed by depositing a first material to partially fill an opening, leaving an unfilled portion with a lower aspect ratio than the original opening. A second material is then deposited to fill the remaining portion of the opening. The first material has good filling characteristics but has higher resistivity than the second material. The second material has low resistivity to give the plug low resistance.

摘要翻译： 通过沉积第一材料以部分地填充开口形成插塞，留下具有比原始开口更低的纵横比的未填充部分。 然后沉积第二种材料以填充开口的剩余部分。 第一种材料具有良好的填充特性，但具有比第二种材料更高的电阻率。 第二种材料具有低电阻率，使插头具有低电阻。

公开(公告)号：US20090251967A1

公开(公告)日：2009-10-08

申请号：US12060956

申请日：2008-04-02

申请人： Masaaki Higashitani

发明人： Masaaki Higashitani

IPC分类号： G11C16/04 ,  H01L21/8247

CPC分类号： H01L29/66825 ,  H01L21/743 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A non-volatile storage device is disclosed that includes a set of connected non-volatile storage elements formed on a well, a bit line contact positioned in the well, a source line contact positioned in the well, a bit line that is connected to the bit line contact, and a source line that is connected to the source line contact and the well.

摘要翻译： 公开了一种非易失性存储装置，其包括形成在阱上的一组连接的非易失性存储元件，位于阱中的位线触点，位于阱中的源极线接触件，连接到该阱的位线 位线接触，以及连接到源极线接触点和阱的源极线。

公开(公告)号：US07569465B2

公开(公告)日：2009-08-04

申请号：US11210218

申请日：2005-08-22

申请人： Jian Chen ,  Masaaki Higashitani

发明人： Jian Chen ,  Masaaki Higashitani

IPC分类号： H01L21/336 ,  H01L21/469

CPC分类号： H01L27/11521 ,  H01L21/7682 ,  H01L23/5222 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： A flash EEPROM or other type of memory cell array having adjacent charge storage elements is formed with a gas filled void between them in order to reduce the level of capacitive coupling between storage elements, thus reducing cross-coupling between charge storage elements and resulting errors occurring in the data read from the array.

摘要翻译： 具有相邻电荷存储元件的快闪EEPROM或其它类型的存储单元阵列在它们之间形成有气体填充的空隙，以便降低存储元件之间的电容耦合的电平，从而减少电荷存储元件之间的交叉耦合和产生的错误 在从数组读取的数据中。

公开(公告)号：US07436703B2

公开(公告)日：2008-10-14

申请号：US11319908

申请日：2005-12-27

申请人： Tuan D. Pham ,  Masaaki Higashitani ,  Hao Fang ,  Gerrit Jan Hemink

发明人： Tuan D. Pham ,  Masaaki Higashitani ,  Hao Fang ,  Gerrit Jan Hemink

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11534

摘要： A NAND flash memory device incorporates a unique booster plate design. The booster plate is biased during read and program operations and the coupling to the floating gates in many cases reduces the voltage levels necessary to program and read the charge stored in the gates. The booster plate also shields against unwanted coupling between floating gates. Self boosting, local self boosting, and erase area self boosting modes used with the unique booster plate further improve read/write reliability and accuracy. A more compact and reliable memory device can hence be realized according to the present invention.

摘要翻译： NAND闪存器件采用独特的增压板设计。 升压板在读取和编程操作期间被偏置，并且在许多情况下与浮动栅极的耦合降低了编程和读取存储在栅极中的电荷所需的电压电平。 升压板还屏蔽浮动栅极之间的不必要的耦合。 自升压，局部自升压，以及独特升压板使用的擦除区域自升压模式，进一步提高了读/写可靠性和精度。 因此，根据本发明可以实现更紧凑和可靠的存储器件。

公开(公告)号：US07362615B2

公开(公告)日：2008-04-22

申请号：US11319260

申请日：2005-12-27

申请人： Tuan D. Pham ,  Masaaki Higashitani ,  Hao Fang ,  Gerrit Jan Hemink

发明人： Tuan D. Pham ,  Masaaki Higashitani ,  Hao Fang ,  Gerrit Jan Hemink

IPC分类号： G11C16/00

CPC分类号： G11C16/0483 ,  H01L23/5222 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11534 ,  H01L2924/0002 ,  H01L2924/00

摘要： A NAND flash memory device incorporates a unique booster plate design. The booster plate is biased during read and program operations and the coupling to the floating gates in many cases reduces the voltage levels necessary to program and read the charge stored in the gates. The booster plate also shields against unwanted coupling between floating gates. Self boosting, local self boosting, and erase area self boosting modes used with the unique booster plate further improve read/write reliability and accuracy. A more compact and reliable memory device can hence be realized according to the present invention.

摘要翻译： NAND闪存器件采用独特的增压板设计。 升压板在读取和编程操作期间被偏置，并且在许多情况下与浮动栅极的耦合降低了编程和读取存储在栅极中的电荷所需的电压电平。 升压板还屏蔽浮动栅极之间的不必要的耦合。 自升压，局部自升压，以及独特升压板使用的擦除区域自升压模式，进一步提高了读/写可靠性和精度。 因此，根据本发明可以实现更紧凑和可靠的存储器件。