公开(公告)号：US20130070530A1

公开(公告)日：2013-03-21

申请号：US13622045

申请日：2012-09-18

申请人： Jian Chen ,  Sergei Gorobets ,  Steven Sprouse ,  Tien-Chien Kuo ,  Yan Li ,  Seungpil Lee ,  Alex Mak ,  Deepanshu Dutta ,  Masaaki Higashitani

发明人： Jian Chen ,  Sergei Gorobets ,  Steven Sprouse ,  Tien-Chien Kuo ,  Yan Li ,  Seungpil Lee ,  Alex Mak ,  Deepanshu Dutta ,  Masaaki Higashitani

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C5/063 ,  G11C11/5628 ,  G11C2211/5641

摘要： A non-volatile storage system is disclosed that includes non-volatile memory cells designed for high endurance and lower retention than other non-volatile memory cells.

摘要翻译： 公开了一种非易失性存储系统，其包括设计用于高耐久性和比其他非易失性存储器单元更低保持性的非易失性存储器单元。

公开(公告)号：US07447086B2

公开(公告)日：2008-11-04

申请号：US11866261

申请日：2007-10-02

申请人： Jun Wan ,  Jeffrey Lutze ,  Masaaki Higashitani ,  Gerrit Jan Hemink ,  Ken Oowada ,  Jian Chen ,  Geoffrey S Gongwer

发明人： Jun Wan ,  Jeffrey Lutze ,  Masaaki Higashitani ,  Gerrit Jan Hemink ,  Ken Oowada ,  Jian Chen ,  Geoffrey S Gongwer

IPC分类号： G11C7/00

CPC分类号： G11C16/3418

摘要： A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. Certain program inhibit schemes have been discovered to better minimize or eliminate program disturb at select word lines. In one embodiment, selecting a program inhibit scheme includes selecting a program voltage pulse ramp rate. Different ramp rates have been discovered to better minimize program disturb when applied to select word lines. In another embodiment, the temperature of a memory system is detected before or during a program operation. A program inhibit scheme can be selected based on the temperature of the system.

摘要翻译： 编程非易失性存储器系统以减少或避免编程干扰。 根据一个实施例，对于单个非易失性存储器系统采用多个程序禁止方案。 基于正在编程的字线选择程序禁止方案。 已经发现某些程序禁止方案能够更好地最小化或消除选择字线上的程序干扰。 在一个实施例中，选择编程禁止方案包括选择编程电压脉冲斜率。 在应用于选择字线时，已经发现了不同的斜率以更好地最小化程序干扰。 在另一个实施例中，在程序操作之前或期间检测存储器系统的温度。 可以基于系统的温度来选择程序禁止方案。

公开(公告)号：US07569465B2

公开(公告)日：2009-08-04

申请号：US11210218

申请日：2005-08-22

申请人： Jian Chen ,  Masaaki Higashitani

发明人： Jian Chen ,  Masaaki Higashitani

IPC分类号： H01L21/336 ,  H01L21/469

CPC分类号： H01L27/11521 ,  H01L21/7682 ,  H01L23/5222 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： A flash EEPROM or other type of memory cell array having adjacent charge storage elements is formed with a gas filled void between them in order to reduce the level of capacitive coupling between storage elements, thus reducing cross-coupling between charge storage elements and resulting errors occurring in the data read from the array.

摘要翻译： 具有相邻电荷存储元件的快闪EEPROM或其它类型的存储单元阵列在它们之间形成有气体填充的空隙，以便降低存储元件之间的电容耦合的电平，从而减少电荷存储元件之间的交叉耦合和产生的错误 在从数组读取的数据中。

公开(公告)号：US06975537B2

公开(公告)日：2005-12-13

申请号：US11049802

申请日：2005-02-03

申请人： Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Masaaki Higashitani

发明人： Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Masaaki Higashitani

IPC分类号： G11C11/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC分类号： G11C16/3418 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3454

摘要： A non-volatile semiconductor memory system (or other type of memory system) is programmed in a manner that avoids program disturb. In one embodiment that includes a flash memory system using a NAND architecture, program disturb is avoided by increasing the channel potential of the source side of the NAND string during the programming process. One exemplar implementation includes applying a voltage (e.g. Vdd) to the source contact and turning on the source side select transistor for the NAND sting corresponding to the cell being inhibited. Another implementation includes applying a pre-charging voltage to the unselected word lines of the NAND string corresponding to the cell being inhibited prior to applying the program voltage.

公开(公告)号：US07045849B2

公开(公告)日：2006-05-16

申请号：US10443502

申请日：2003-05-21

申请人： Jian Chen ,  Masaaki Higashitani

发明人： Jian Chen ,  Masaaki Higashitani

IPC分类号： H01L29/76 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/7682 ,  H01L23/5222 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： A flash EEPROM or other type of memory cell array having adjacent charge storage elements is formed with a gas filled void between them in order to reduce the level of capacitive coupling between storage elements, thus reducing cross-coupling between charge storage elements and resulting errors occurring in the data read from the array.

公开(公告)号：US20080019180A1

公开(公告)日：2008-01-24

申请号：US11866261

申请日：2007-10-02

申请人： Jun Wan ,  Jeffrey Lutze ,  Masaaki Higashitani ,  Gerrit Hemink ,  Ken Oowada ,  Jian Chen ,  Geoffrey Gongwer

发明人： Jun Wan ,  Jeffrey Lutze ,  Masaaki Higashitani ,  Gerrit Hemink ,  Ken Oowada ,  Jian Chen ,  Geoffrey Gongwer

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/3418

摘要： A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. Certain program inhibit schemes have been discovered to better minimize or eliminate program disturb at select word lines. In one embodiment, selecting a program inhibit scheme includes selecting a program voltage pulse ramp rate. Different ramp rates have been discovered to better minimize program disturb when applied to select word lines. In another embodiment, the temperature of a memory system is detected before or during a program operation. A program inhibit scheme can be selected based on the temperature of the system.

摘要翻译： 编程非易失性存储器系统以减少或避免编程干扰。 根据一个实施例，对于单个非易失性存储器系统采用多个程序禁止方案。 基于正在编程的字线选择程序禁止方案。 已经发现某些程序禁止方案能够更好地最小化或消除选择字线上的程序干扰。 在一个实施例中，选择编程禁止方案包括选择编程电压脉冲斜率。 在应用于选择字线时，已经发现了不同的斜率以更好地最小化程序干扰。 在另一个实施例中，在程序操作之前或期间检测存储器系统的温度。 可以基于系统的温度来选择程序禁止方案。

公开(公告)号：US07295478B2

公开(公告)日：2007-11-13

申请号：US11127743

申请日：2005-05-12

申请人： Jun Wan ,  Jeffrey Lutze ,  Masaaki Higashitani ,  Gerrit Jan Hemink ,  Ken Oowada ,  Jian Chen ,  Geoffrey S. Gongwer

发明人： Jun Wan ,  Jeffrey Lutze ,  Masaaki Higashitani ,  Gerrit Jan Hemink ,  Ken Oowada ,  Jian Chen ,  Geoffrey S. Gongwer

IPC分类号： G11C7/00

CPC分类号： G11C16/3418

摘要： A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. Certain program inhibit schemes have been discovered to better minimize or eliminate program disturb at select word lines. In one embodiment, selecting a program inhibit scheme includes selecting a program voltage pulse ramp rate. Different ramp rates have been discovered to better minimize program disturb when applied to select word lines. In another embodiment, the temperature of a memory system is detected before or during a program operation. A program inhibit scheme can be selected based on the temperature of the system.

摘要翻译： 编程非易失性存储器系统以减少或避免编程干扰。 根据一个实施例，对于单个非易失性存储器系统采用多个程序禁止方案。 基于正在编程的字线选择程序禁止方案。 已经发现某些程序禁止方案能够更好地最小化或消除选择字线上的程序干扰。 在一个实施例中，选择编程禁止方案包括选择编程电压脉冲斜率。 在应用于选择字线时，已经发现了不同的斜率以更好地最小化程序干扰。 在另一个实施例中，在程序操作之前或期间检测存储器系统的温度。 可以基于系统的温度来选择程序禁止方案。

公开(公告)号：US20060279990A1

公开(公告)日：2006-12-14

申请号：US11127743

申请日：2005-05-12

申请人： Jun Wan ,  Jeffrey Lutze ,  Masaaki Higashitani ,  Gerrit Hemink ,  Ken Oowada ,  Jian Chen ,  Geoffrey Gongwer

发明人： Jun Wan ,  Jeffrey Lutze ,  Masaaki Higashitani ,  Gerrit Hemink ,  Ken Oowada ,  Jian Chen ,  Geoffrey Gongwer

IPC分类号： G11C16/04

CPC分类号： G11C16/3418

摘要： A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. Certain program inhibit schemes have been discovered to better minimize or eliminate program disturb at select word lines. In one embodiment, selecting a program inhibit scheme includes selecting a program voltage pulse ramp rate. Different ramp rates have been discovered to better minimize program disturb when applied to select word lines. In another embodiment, the temperature of a memory system is detected before or during a program operation. A program inhibit scheme can be selected based on the temperature of the system.

摘要翻译： 编程非易失性存储器系统以减少或避免编程干扰。 根据一个实施例，对于单个非易失性存储器系统采用多个程序禁止方案。 基于正在编程的字线选择程序禁止方案。 已经发现某些程序禁止方案能够更好地最小化或消除选择字线上的程序干扰。 在一个实施例中，选择编程禁止方案包括选择编程电压脉冲斜率。 在应用于选择字线时，已经发现了不同的斜率以更好地最小化程序干扰。 在另一个实施例中，在程序操作之前或期间检测存储器系统的温度。 可以基于系统的温度来选择程序禁止方案。

公开(公告)号：US20050128810A1

公开(公告)日：2005-06-16

申请号：US11049802

申请日：2005-02-03

申请人： Jeffrey Lutze ,  Jian Chen ,  Yan Li ,  Masaaki Higashitani

发明人： Jeffrey Lutze ,  Jian Chen ,  Yan Li ,  Masaaki Higashitani

IPC分类号： G11C11/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC分类号： G11C16/3418 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3454

摘要： A non-volatile semiconductor memory system (or other type of memory system) is programmed in a manner that avoids program disturb. In one embodiment that includes a flash memory system using a NAND architecture, program disturb is avoided by increasing the channel potential of the source side of the NAND string during the programming process. One exemplar implementation includes applying a voltage (e.g. Vdd) to the source contact and turning on the source side select transistor for the NAND sting corresponding to the cell being inhibited. Another implementation includes applying a pre-charging voltage to the unselected word lines of the NAND string corresponding to the cell being inhibited prior to applying the program voltage.

摘要翻译： 以避免程序干扰的方式编程非易失性半导体存储器系统（或其他类型的存储器系统）。 在包括使用NAND架构的闪存系统的一个实施例中，通过在编程处理期间增加NAND串的源侧的沟道电位来避免程序干扰。 一个示例性实施方案包括将电压（例如Vdd）施加到源极触点，并且接通源抑制对应的单元的NAND极的源极侧选择晶体管。 另一种实施方案包括在施加编程电压之前，将预充电电压施加到对应于被禁止的单元的NAND串的未选择字线。

公开(公告)号：US06859397B2

公开(公告)日：2005-02-22

申请号：US10379608

申请日：2003-03-05

申请人： Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Masaaki Higashitani

发明人： Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Masaaki Higashitani

IPC分类号： G11C11/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC分类号： G11C16/3418 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3454

摘要： A non-volatile semiconductor memory system (or other type of memory system) is programmed in a manner that avoids program disturb. In one embodiment that includes a flash memory system using a NAND architecture, program disturb is avoided by increasing the channel potential of the source side of the NAND string during the programming process. One exemplar implementation includes applying a voltage (e.g. Vdd) to the source contact and turning on the source side select transistor for the NAND sting corresponding to the cell being inhibited. Another implementation includes applying a pre-charging voltage to the unselected word lines of the NAND string corresponding to the cell being inhibited prior to applying the program voltage.

摘要翻译： 以避免程序干扰的方式编程非易失性半导体存储器系统（或其他类型的存储器系统）。 在包括使用NAND架构的闪存系统的一个实施例中，通过在编程处理期间增加NAND串的源侧的沟道电位来避免程序干扰。 一个示例性实施方案包括将电压（例如Vdd）施加到源极触点，并接通源极侧选择晶体管，用于对应于被抑制的电池的NAND触发。 另一种实施方案包括在施加编程电压之前，将预充电电压施加到对应于被禁止的单元的NAND串的未选择字线。