公开(公告)号：US20230057852A1

公开(公告)日：2023-02-23

申请号：US17408813

申请日：2021-08-23

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  M. Jared Barclay ,  Bhavesh Bhartia ,  Chet E. Carter ,  John D. Hopkins ,  Andrew Li ,  Haoyu Li ,  Alyssa N. Scarbrough ,  Grady S. Waldo

IPC: H01L27/11582 ,  H01L27/11556

Abstract: Integrated circuitry comprising a memory array comprises strings of memory cells comprising laterally-spaced memory blocks individually comprising a first vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier. The conductive tiers individually comprise a horizontally-elongated conductive line. A second vertical stack is aside the first vertical stack. The second vertical stack comprises an upper portion and a lower portion. The upper portion comprises vertically-alternating first insulating tiers and second insulating tiers that are of different insulative compositions relative one another. The lower portion comprises a horizontal line above the conductor tier that runs parallel with the laterally-spaced memory blocks in the first vertical stack. Other embodiments, including method, are disclosed.

公开(公告)号：US20230055319A1

公开(公告)日：2023-02-23

申请号：US17409300

申请日：2021-08-23

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  John D. Hopkins ,  Collin Howder ,  Jordan D. Greenlee

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11582

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions. Material of the first tiers is of different composition from material of the second tiers. The lower portion comprises an upper second tier comprising insulative material. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion. Channel-material strings are formed that extend through the upper portion to the lower portion. Horizontally-elongated lines are formed in the upper second tier longitudinally-along opposing lateral edges of the memory-block regions. Material of the lines is of different composition. from that of the insulative material in the upper second tier that is laterally-between the lines. Horizontally-elongated trenches are formed into the stack that are individually between immediately-laterally-adjacent of the memory-block regions and that extend through the upper portion to the lower portion. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US11545430B2

公开(公告)日：2023-01-03

申请号：US17070269

申请日：2020-10-14

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  John D. Hopkins ,  Alyssa N. Scarbrough

IPC: H01L29/76 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11556

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A lower portion of a stack is formed, with the stack ultimately comprising vertically-alternating first tiers and second tiers above the conductor tier. The stack comprises laterally-spaced memory-block regions. Material of the first tiers is of different composition from material of the second tiers. A lowest of the first tiers comprises conductive first sacrificial material. Conductive second material is directly electrically coupled to the conductive first sacrificial material. The conductive first sacrificial material and the conductive second material have different reduction potentials that are at least 0.5V away from one another. A lowest of the second tiers is insulative and below the lowest first tier. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion. Channel-material strings are formed that extend through the first tiers and the second tiers in the upper portion to the lowest first tier in the lower portion. Horizontally-elongated trenches are formed into the stack that are individually between immediately-laterally-adjacent of the memory-block regions and extend to the conductive first sacrificial material and the conductive second material in the lowest first tier. The conductive first sacrificial material is galvanically etched through the trenches. The lowest second tier is removed after the galvanically etching. After removing the lowest second tier, conducting material is formed in the lowest first tier that directly electrically couples together the channel material of the individual channel-material strings and the conductor material of the conductor tier. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US11527550B2

公开(公告)日：2022-12-13

申请号：US17177357

申请日：2021-02-17

Applicant: Micron Technology, Inc.

Inventor： Changhan Kim ,  Richard J. Hill ,  John D. Hopkins ,  Collin Howder

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L21/28

Abstract: A memory array comprises a vertical stack comprising alternating insulative tiers and wordline tiers. The wordline tiers comprise gate regions of individual memory cells. The gate regions individually comprise part of a wordline in individual of the wordline tiers. Channel material extends elevationally through the insulative tiers and the wordline tiers. The individual memory cells comprise a memory structure laterally between the gate region and the channel material. Individual of the wordlines comprise opposing laterally-outer longitudinal edges. The longitudinal edges individually comprise a longitudinally-elongated recess extending laterally into the respective individual wordline. Methods are disclosed.

公开(公告)号：US11495610B2

公开(公告)日：2022-11-08

申请号：US16921641

申请日：2020-07-06

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Shyam Surthi ,  Matthew Thorum

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11524

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. The second tiers comprise doped silicon dioxide and the first tiers comprise a material other than doped silicon dioxide. The stack comprises laterally-spaced memory-block regions. Channel-material-string constructions extend through the first tiers and the second tiers in the memory-block regions. The doped silicon dioxide that is in the second tiers is etched selectively relative to said other material that is in the first tiers and selectively relative to and to expose an undoped silicon dioxide-comprising string of a charge-blocking material that is part of individual of the channel-material-string constructions. Structure independent of method is disclosed.

公开(公告)号：US20220199645A1

公开(公告)日：2022-06-23

申请号：US17692004

申请日：2022-03-10

Applicant: Micron Technology, Inc.

Inventor： Changhan Kim ,  Chet E. Carter ,  Cole Smith ,  Collin Howder ,  Richard J. Hill ,  Jie Li

IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11568 ,  H01L29/51 ,  H01L29/49 ,  H01L21/311 ,  H01L21/02 ,  H01L27/11521 ,  H01L27/11556 ,  H01L29/788 ,  H01L29/792 ,  H01L29/66 ,  H01L29/10 ,  H01L21/28 ,  H01L27/11529 ,  H01L27/1157

Abstract: Some embodiments include a method of forming an assembly (e.g., a memory array). A first opening is formed through a stack of alternating first and second levels. The first levels contain silicon nitride, and the second levels contain silicon dioxide. Some of the silicon dioxide of the second levels is replaced with memory cell structures. The memory cell structures include charge-storage regions adjacent charge-blocking regions. Tunneling material is formed within the first opening, and channel material is formed adjacent the tunneling material. A second opening is formed through the stack. The second opening extends through remaining portions of the silicon dioxide, and through the silicon nitride. The remaining portions of the silicon dioxide are removed to form cavities. Conductive regions are formed within the cavities. The silicon nitride is removed to form voids between the conductive regions. Some embodiments include memory arrays.

公开(公告)号：US11355392B2

公开(公告)日：2022-06-07

申请号：US16987991

申请日：2020-08-07

Applicant: Micron Technology, Inc.

Inventor： Yiping Wang ,  Jordan D. Greenlee ,  Collin Howder

IPC: H01L21/768 ,  H01L23/522 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11582

Abstract: A method used in forming a conductive via of integrated circuitry comprises forming a lining laterally over sidewalk of an elevationally-elongated opening. The lining comprises elemental-form silicon. The elemental-form silicon of an uppermost portion of the lining is ion implanted in the elevationally-elongated opening. The ion-implanted elemental-form silicon of the uppermost portion of the lining is etched selectively relative to the elemental-form silicon of a lower portion of the lining below the uppermost portion that was not subjected to said ion implanting. The elemental-form silicon of the lower portion of the lining is reacted with a metal halide to form elemental-form metal in a lower portion of the elevationally-elongated opening that is the metal from the metal halide. Conductive material in the elevationally-elongated opening is formed atop and directly against the elemental-form metal. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US11335694B2

公开(公告)日：2022-05-17

申请号：US16702255

申请日：2019-12-03

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Chet E. Carter

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524 ,  H01L21/822

Abstract: A method used in forming a memory array comprises forming a substrate comprising a conductor tier comprising an upper conductor material and a lower conductor material, and a stack comprising vertically-alternating first tiers and second tiers above the conductor tier. Horizontally-elongated trenches are formed through the stack to the upper conductor material and the lower conductor material. At least one of the upper and lower conductor materials have an exposed catalytic surface in the trenches. Metal material is electrolessly deposited onto the catalytic surface to cover the upper conductor material and the lower conductor material within the trenches. Channel-material strings of memory cells are formed and extend through the second tiers and the first tiers. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US11276701B2

公开(公告)日：2022-03-15

申请号：US16787914

申请日：2020-02-11

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Chet E. Carter

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11519

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers above a substrate. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. Catalytic material is formed in a bottom region of individual of the trenches. Metal material is electrolessly deposited onto a catalytic surface of the catalytic material to individually fill at least a majority of remaining volume of the individual trenches. Channel-material strings are formed and extend through the first tiers and the second tiers. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20220068800A1

公开(公告)日：2022-03-03

申请号：US17070269

申请日：2020-10-14

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  John D. Hopkins ,  Alyssa N. Scarbrough

IPC: H01L23/522 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A lower portion of a stack is formed, with the stack ultimately comprising vertically-alternating first tiers and second tiers above the conductor tier. The stack comprises laterally-spaced memory-block regions. Material of the first tiers is of different composition from material of the second tiers. A lowest of the first tiers comprises conductive first sacrificial material. Conductive second material is directly electrically coupled to the conductive first sacrificial material. The conductive first sacrificial material and the conductive second material have different reduction potentials that are at least 0.5V away from one another. A lowest of the second tiers is insulative and below the lowest first tier. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion. Channel-material strings are formed that extend through the first tiers and the second tiers in the upper portion to the lowest first tier in the lower portion. Horizontally-elongated trenches are formed into the stack that are individually between immediately-laterally-adjacent of the memory-block regions and extend to the conductive first sacrificial material and the conductive second material in the lowest first tier. The conductive first sacrificial material is galvanically etched through the trenches. The lowest second tier is removed after the galvanically etching. After removing the lowest second tier, conducting material is formed in the lowest first tier that directly electrically couples together the channel material of the individual channel-material strings and the conductor material of the conductor tier. Other embodiments, including structure independent of method, are disclosed.