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公开(公告)号：US10861529B2
公开(公告)日：2020-12-08
申请号：US16387227
申请日：2019-04-17
Applicant: Micron Technology, Inc.
Inventor： Riccardo Muzzetto
Abstract: Methods, systems, and apparatuses for self-referencing sensing schemes are described. A cell having two transistors, or other switching components, and one capacitor, such as a ferroelectric capacitor, may be sensed using a reference value that is specific to the cell. The cell may be read and sampled via one access line, and the cell may be used to generate a reference voltage and sampled via another access line. For instance, a first access line of a cell may be connected to one read voltage while a second access line of the cell is isolated from a voltage source; then the second access line may be connected to another read voltage while the first access line is isolate from a voltage source. The resulting voltages on the respective access lines may be compared to each other and a logic value of the cell determined from the comparison.
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公开(公告)号：US10446214B1
公开(公告)日：2019-10-15
申请号：US16102053
申请日：2018-08-13
Applicant: Micron Technology, Inc.
Inventor： Umberto Di Vincenzo , Ferdinando Bedeschi , Riccardo Muzzetto
IPC: G11C11/22
Abstract: Methods and devices for reading a memory cell using a sense amplifier with split capacitors is described. The sense amplifier may include a first capacitor and a second capacitor that may be configured to provide a larger capacitance during certain portions of a read operation and a lower capacitance during other portions of the read operation. In some cases, the first capacitor and the second capacitor are configured to be coupled in parallel between a signal node and a voltage source during a first portion of the read operation to provide a higher capacitance. The first capacitor may be decoupled from the second capacitor during a second portion of the read operation to provide a lower capacitance during the second portion.
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公开(公告)号：US20190189211A1
公开(公告)日：2019-06-20
申请号：US15846373
申请日：2017-12-19
Applicant: Micron Technology, Inc.
Inventor： Umberto Di Vincenzo , Riccardo Muzzetto , Ferdinando Bedeschi
CPC classification number: G11C14/0027 , G11C11/221 , G11C11/2273 , G11C11/2293
Abstract: The present disclosure includes apparatuses, methods, and systems for charge separation for memory sensing. An embodiment includes applying a sensing voltage to a memory cell, and determining a data state of the memory cell based, at least in part, on a comparison of an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell before a particular reference time and an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell after the particular reference time.
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公开(公告)号：US20190066753A1
公开(公告)日：2019-02-28
申请号：US15687019
申请日：2017-08-25
Applicant: Micron Technology, Inc.
Inventor： Riccardo Muzzetto
IPC: G11C11/22
CPC classification number: G11C11/2259 , G11C11/221 , G11C11/2257 , G11C11/2273 , G11C11/2275
Abstract: Self-referencing memory device, techniques, and methods are described herein. A self-referencing memory device may include a ferroelectric memory cell. The self-referencing memory device may be configured to determine a logic state stored in a memory cell based on a state signal generated using the ferroelectric memory cell and a reference signal generated using the ferroelectric memory cell. The biasing of the plate line of the ferroelectric memory cell may be used to generate the voltage need to generate the state signal during a first time period of an access operation and to generate the reference signal during a second time period of the access operation. Procedures and operations related to a self-referencing memory device are described.
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公开(公告)号：US12288591B2
公开(公告)日：2025-04-29
申请号：US17802009
申请日：2021-03-02
Applicant: Micron Technology, Inc.
Inventor： Christophe Laurent , Riccardo Muzzetto
IPC: G01R31/317 , G01R31/3177 , G01R31/3185 , G06F11/26 , G06F11/267 , G06F11/27 , G06F11/34 , G11C29/42 , G11C29/52
Abstract: The present disclosure relates to a memory device comprising an array of memory cells and an operating circuit for managing the operation of the array, the operating circuit comprising an encoding unit configured to generate a codeword, the codeword comprising payload data stored in a plurality of memory cells of the array, parity data associated with the payload data stored in parity cells of the memory array, wherein a number of parity cells to be used to store the parity data is selectable based on a status of the plurality of memory cells and is related to a selected Error Correction Code (ECC) protection level, and extra payload data stored in unused parity cells, the device further comprising a decoding unit configured to perform an ECC operation on the stored codeword based on the selected ECC protection level. The encoding unit and the decoding unit comprise respective circuit portions configured to be selectively activable based on the selected ECC protection level, and each circuit portion is configured to manage a respective predetermined payload and parity quantity of the codeword.
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Patent Agency Ranking
公开(公告)号：US12266410B2
公开(公告)日：2025-04-01
申请号：US17801467
申请日：2021-03-02
Applicant: Micron Technology, Inc.
Inventor： Christophe Laurent , Riccardo Muzzetto
Abstract: The present disclosure relates to operating an array of memory cells, including storing user data in a plurality of memory cells of the memory array, storing parity data associated with the user data in parity cells of the memory array, in which a number of used parity cells is selected based on a status of the memory cells and is related to a selected Error Correction Code (ECC) correction capability, and performing an ECC operation on the plurality of memory cells, the ECC correction capability being based on the selected number of used parity cells. Related memory devices and systems are also herein disclosed.
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公开(公告)号：US20250061023A1
公开(公告)日：2025-02-20
申请号：US18936548
申请日：2024-11-04
Applicant: Micron Technology, Inc.
Inventor： Graziano Mirichigni , Christophe Laurent , Riccardo Muzzetto
Abstract: The present disclosure relates to a method for operating an array of memory cells, the method comprising storing user data in a plurality of memory cells of the array, storing parity data associated with the user data in a plurality of parity cells of the array, and, based on the stored parity data, selecting an Error Correction Code (ECC) correction capability and/or an ECC granularity according to which an ECC operation is to be performed, wherein the selection of the ECC correction capability and/or the ECC granularity is determined by the steps of updating a first register, said first register comprising values which indicate a required ECC correction capability and/or a required ECC granularity to be applied to the memory cells based on a current status of said memory cells, wherein the values of the first register are updated based on a variation of the current status of the memory cells, and wherein an update of the values of the first register corresponds to a variation of the required ECC correction capability and/or a required ECC granularity to be applied to said memory cells, and based on the updated values of the first register, executing an ECC switch command, wherein the ECC switch command is such as to vary a previously selected ECC correction capability and/or a previously selected ECC granularity, the method further comprising: updating a second register according to the varied ECC correction capability and/or ECC granularity, said second register comprising values indicating the selected ECC correction capability and the selected ECC granularity applied to the memory cells based on the current status thereof. Related apparatuses and systems are also herein disclosed.
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公开(公告)号：US20240419548A1
公开(公告)日：2024-12-19
申请号：US18821642
申请日：2024-08-30
Applicant: Micron Technology, Inc.
Inventor： Christophe Laurent , Riccardo Muzzetto
IPC: G06F11/10
Abstract: The present disclosure relates to defining a minimum number of parity cells for storing parity data, the minimum number of parity cells corresponding to a minimum Error Correction Code (ECC) correction capability, defining a maximum number of parity cells for storing the parity data, the maximum number of parity cells corresponding to a maximum ECC correction capability, storing payload content in a plurality of memory cells of a memory array, and, based on a current status of the memory cells storing the payload, selecting a number of parity cells to be used for storing the parity data between the minimum number and the maximum number. The payload is stored in at least part of the parity cells which are not selected to store parity data. Related memory devices and systems are also herein disclosed.
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公开(公告)号：US20240412768A1
公开(公告)日：2024-12-12
申请号：US18808718
申请日：2024-08-19
Applicant: Micron Technology, Inc.
Inventor： Christophe Laurent , Riccardo Muzzetto
Abstract: The present disclosure includes apparatuses, methods, and systems for unbalanced programmed data states in memory. An embodiment includes a memory having a group of memory cells, and circuitry configured to determine a quantity of the memory cells of the group to program to a first data state, wherein the determined quantity of memory cells is less than or greater than half of the memory cells of the group, program the determined quantity of the memory cells of the group to the first data state, and program a remaining quantity of the memory cells of the group to a second data state.
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公开(公告)号：US12135610B2
公开(公告)日：2024-11-05
申请号：US17802053
申请日：2021-09-23
Applicant: Micron Technology, Inc.
Inventor： Graziano Mirichigni , Christophe Laurent , Riccardo Muzzetto
Abstract: The present disclosure relates to a method for operating an array of memory cells, the method comprising storing user data in a plurality of memory cells of the array, storing parity data associated with the user data in a plurality of parity cells of the array, and, based on the stored parity data, selecting an Error Correction Code (ECC) correction capability and/or an ECC granularity according to which an ECC operation is to be performed, wherein the selection of the ECC correction capability and/or the ECC granularity is determined by the steps of updating a first register, said first register comprising values which indicate a required ECC correction capability and/or a required ECC granularity to be applied to the memory cells based on a current status of said memory cells, wherein the values of the first register are updated based on a variation of the current status of the memory cells, and wherein an update of the values of the first register corresponds to a variation of the required ECC correction capability and/or a required ECC granularity to be applied to said memory cells, and based on the updated values of the first register, executing an ECC switch command, wherein the ECC switch command is such as to vary a previously selected ECC correction capability and/or a previously selected ECC granularity, the method further comprising: updating a second register according to the varied ECC correction capability and/or ECC granularity, said second register comprising values indicating the selected ECC correction capability and the selected ECC granularity applied to the memory cells based on the current status thereof. Related apparatuses and systems are also herein disclosed.
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