公开(公告)号：US06508126B2

公开(公告)日：2003-01-21

申请号：US09897016

申请日：2001-07-03

申请人： Minekazu Sakai ,  Seiki Aoyama ,  Hirotsugu Funato

发明人： Minekazu Sakai ,  Seiki Aoyama ,  Hirotsugu Funato

IPC分类号： G01P15125

CPC分类号： G01P15/0802 ,  G01P15/125 ,  G01P21/00 ,  G01P2015/0814

摘要： A dynamic quantity sensor has a weigh portion that is supported by a base portion to be displaced by a dynamic quantity, a movable electrode protruding from the weigh portion, and a fixed electrode protruding from the base portion and defining a detection interval with the movable electrode. The detection interval changes in response to displacement of the weight portion for detecting the dynamic quantity. Each of the movable electrode and the fixed electrode has a tapered plane shape with a width that decreases from a root portion toward a tip portion thereof.

公开(公告)号：US06373093B1

公开(公告)日：2002-04-16

申请号：US09776769

申请日：2001-02-06

申请人： Tetsuo Fujii ,  Minekazu Sakai ,  Akira Kuroyanagi

发明人： Tetsuo Fujii ,  Minekazu Sakai ,  Akira Kuroyanagi

IPC分类号： H01L2976

摘要： A gate oxide film is formed on a surface of a semiconductor substrate. A tunnel insulating film having a thickness smaller than that of the gate insulating film is formed in a portion thereof corresponding to a tunnel region. A first silicon film having a low impurity concentration is formed on the gate insulating film. A second silicon film having an impurity concentration higher than that of the first silicon film is formed on the first silicon film so as to be connected thereto. A third silicon film is formed on the second silicon film through an insulating film. The second and third silicon films are formed into floating and control gates, respectively, thereby forming a semiconductor memory device.

公开(公告)号：US06194236B1

公开(公告)日：2001-02-27

申请号：US09247908

申请日：1999-02-11

申请人： Minekazu Sakai ,  Tsuyoshi Fukada ,  Yukihiko Tanizawa ,  Koki Mizuno ,  Yasutoshi Suzuki ,  Yoshitsugu Abe ,  Hiroshi Tanaka ,  Motoki Ito ,  Kazuhisa Ikeda ,  Hiroshi Okada

发明人： Minekazu Sakai ,  Tsuyoshi Fukada ,  Yukihiko Tanizawa ,  Koki Mizuno ,  Yasutoshi Suzuki ,  Yoshitsugu Abe ,  Hiroshi Tanaka ,  Motoki Ito ,  Kazuhisa Ikeda ,  Hiroshi Okada

IPC分类号： H01L2166

CPC分类号： G01L9/0042 ,  H01L29/84 ,  Y10S438/977

摘要： An etching method for a silicon substrate, which can easily smooth the etching surface of the (110)-oriented silicon, is disclosed. A container is filled with KOH solution. In the KOH solution is immersed a (110)-oriented silicon wafer having a PN junction and is also disposed a platinum electrode plate to face the silicon wafer. To between a platinum electrode of the silicon wafer and the platinum electrode plate are connected a constant voltage power source, an ammeter and a contact in series. A controller starts etching from one surface on which the PN junction is formed, and terminates voltage application when the specified time lapses after the formation of an anodic oxide film is equilibrated with the etching of the anodic oxide film on the etching surface on the PN junction part. In this case, the controller detects flowing current through the ammeter, and the point of time when the equilibrium state is obtained is the point of inflection of the detected current to the constant current after the peak thereof.

摘要翻译： 公开了一种可以容易地平滑（110）取向的硅的蚀刻表面的硅衬底的蚀刻方法。 容器中充满KOH溶液。 在KOH溶液中浸渍具有PN结的（110）取向的硅晶片，并且还设置有与铂晶片相对的铂电极板。 在硅晶片的铂电极和铂电极板之间连接恒压电源，电流表和触点串联。 控制器从其上形成PN结的一个表面开始蚀刻，并且在阳极氧化膜形成之后指定的时间经过平衡后，在PN结的蚀刻表面上蚀刻阳极氧化膜来终止电压施加 部分。 在这种情况下，控制器检测通过电流表的流动电流，并且获得平衡状态的时间点是检测电流在其峰值之后的恒定电流的拐点。

公开(公告)号：US6020618A

公开(公告)日：2000-02-01

申请号：US758259

申请日：1996-11-27

申请人： Minekazu Sakai

发明人： Minekazu Sakai

IPC分类号： H01L21/3063 ,  H01L29/82 ,  H01L29/06

CPC分类号： H01L21/3063

摘要： A semiconductor device such as a semiconductor dynamic sensor which is produced at an improved chip yield is provided. Etching wiring having a main line and a branch line is formed on a chip region via an intervening insulating film. The chip region contains an N-type reduced thickness region and is surrounded by a P-type chip isolating layer. The etching wiring is formed with a gap (an etching wiring gap) from other etching wiring members or circuit wiring formed on the chip region via an intervening insulating film. The etching wiring gap is greater than any of the gaps between members of the circuit wiring.

摘要翻译： 提供了以提高的芯片产量生产的诸如半导体动态传感器的半导体器件。 通过中间绝缘膜在芯片区域上形成具有主线和分支线的蚀刻布线。 芯片区域包含N型缩小厚度的区域，被P型芯片隔离层包围。 蚀刻布线形成有与其它蚀刻布线构件或通过中间绝缘膜形成在芯片区域上的电路布线的间隙（蚀刻布线间隙）。 蚀刻布线间隙大于电路布线的构件之间的任何间隙。

公开(公告)号：US5920106A

公开(公告)日：1999-07-06

申请号：US987500

申请日：1997-12-09

申请人： Nobukazu Oba ,  Toshio Ikuta ,  Minekazu Sakai ,  Tsuyoshi Fukada ,  Yasutoshi Suzuki

发明人： Nobukazu Oba ,  Toshio Ikuta ,  Minekazu Sakai ,  Tsuyoshi Fukada ,  Yasutoshi Suzuki

IPC分类号： G01L9/04 ,  B81B3/00 ,  G01L9/00 ,  H01L29/84

CPC分类号： G01L9/0042

摘要： A semiconductor pressure detection device includes a diaphragm formed at a portion of a P- conductivity type semiconductor substrate having a reduced thickness. Gauge resistors are formed on the surface of an N- conductivity type semiconductor layer formed on the substrate. An N+ conductivity type diffusion layer is formed in the N- conductivity type semiconductor layer to fix the electric potential of the N- conductivity type layer. The first conductivity type area surrounds the diaphragm. Therefore, when the N- conductivity type area is supplied with electric potential, the potential gradient in the N- conductivity type layer is small. Thus, the leakage current which flows to a pn junction between the gauge resistors and the N- conductivity type area is reduced.

摘要翻译： 半导体压力检测装置包括形成在具有减小的厚度的P-导电型半导体衬底的部分处的膜片。 在基板上形成的N-导电型半导体层的表面上形成有规格电阻。 在N导电型半导体层中形成N +导电型扩散层，以固定N-导电型层的电位。 第一导电类型区域围绕隔膜。 因此，当N-导电类型区域被提供电位时，N-导电类型层中的电位梯度小。 因此，流向量规电阻器与N-导电型区域之间的pn结的漏电流减小。

公开(公告)号：US5677248A

公开(公告)日：1997-10-14

申请号：US415373

申请日：1995-03-29

申请人： Minekazu Sakai ,  Tsuyoshi Fukada ,  Nobukazu Ohba

发明人： Minekazu Sakai ,  Tsuyoshi Fukada ,  Nobukazu Ohba

IPC分类号： B81C99/00 ,  H01L21/3063 ,  H01L21/78 ,  H01L21/465

CPC分类号： B81C1/00214 ,  H01L21/3063 ,  H01L21/78 ,  Y10S438/977

摘要： The electrochemical stop etching is favorably carried out by the application of any voltage without permitting current that is caused by aluminum remainder to leak and avoiding short-circuits between the low-resistance layer in the scribe region and the isolation. In a method of producing semiconductor devices relying upon the electrochemical stop etching, major circuits are constituted and ground aluminum wirings 5 are formed on at least one surface of a substrate 7, and their peripheries are surrounded by scribe regions to form a plurality of chip patterns 1. On the same surface of the substrate 7 where chip patterns 1 are formed, aluminum wirings 3 for etching are formed via a field oxide film 10 while maintaining a predetermined gap relative to the GND aluminum wirings and maintaining an equal height and surrounding the chip patterns 1 in the scribe regions. The neighboring aluminum wirings 3 for etching are electrically connected together among the chip patterns 1 that neighbor one another, and a predetermined voltage is applied to the aluminum wirings 3 for etching to effect the electrochemical stop etching.

摘要翻译： 电化学停止蚀刻有利地通过施加任何电压而进行，而不允许由铝余量引起的电流泄漏并避免划线区域中的低电阻层与隔离之间的短路。 在依赖于电化学停止蚀刻的半导体器件的制造方法中，构成主要电路，并且在衬底7的至少一个表面上形成接地的铝布线5，并且它们的外围被划线区域包围以形成多个芯片图案 在形成芯片图案1的基板7的相同表面上，用于蚀刻的铝布线3经由场氧化膜10形成，同时保持相对于GND铝布线的预定间隙并保持相等的高度并围绕芯片 模式1在划痕区域。 用于蚀刻的相邻铝布线3在彼此相邻的芯片图案1之间电连接在一起，并且将预定电压施加到铝布线3用于蚀刻以实现电化学停止蚀刻。

公开(公告)号：US5643803A

公开(公告)日：1997-07-01

申请号：US122164

申请日：1993-09-17

申请人： Tsuyoshi Fukada ,  Yoshimi Yoshino ,  Hiroshige Sugito ,  Minekazu Sakai

发明人： Tsuyoshi Fukada ,  Yoshimi Yoshino ,  Hiroshige Sugito ,  Minekazu Sakai

IPC分类号： G01P15/08 ,  G01P15/12 ,  H01L21/3063 ,  C25F3/12

CPC分类号： G01P15/0802 ,  G01P15/123 ,  G01P15/124 ,  H01L21/3063 ,  Y10S438/924

摘要： It is intended to provide an etching method for semiconductor devices in which the etching depth or the thickness of a thin thickness portion can be precisely controlled. According to experiment results, when a P-type substrate in which an N-type epitaxial layer is formed is immersed in an etching solution such as KOH or the like, and a voltage for reverse bias of PN junction is applied between an electrode plate opposing the substrate and the epitaxial layer to perform electrochemical etching, it has been found that the distance from the PN junction plane to the etching stop position is approximately equal to a depletion layer width at the substrate side of the PN junction portion. Namely, the etching stops at the forward end of the depletion layer. Therefore, the junction depletion layer width at the substrate side is controlled to be a size obtained by subtracting a necessary depth for etching from a thickness of the semiconductor substrate except for the semiconductor layer, so that the etching depth or the thickness of the thin thickness portion remaining after etching can be precisely controlled.

摘要翻译： 旨在为半导体器件提供蚀刻方法，其中可以精确地控制蚀刻深度或厚度厚度部分的厚度。 根据实验结果，当将形成有N型外延层的P型衬底浸入诸如KOH等的蚀刻溶液中时，将PN结的反向偏压施加在相对的电极板之间 衬底和外延层进行电化学蚀刻，已经发现从PN结面到蚀刻停止位置的距离近似等于PN结部分的衬底侧的耗尽层宽度。 也就是说，蚀刻在耗尽层的前端停止。 因此，将衬底侧的结耗尽层宽度控制为通过从除了半导体层之外的半导体衬底的厚度减去所需的蚀刻深度获得的尺寸，使得蚀刻深度或厚度厚度 可以精确地控制蚀刻后残留的部分。

公开(公告)号：US5549785A

公开(公告)日：1996-08-27

申请号：US120380

申请日：1993-09-14

申请人： Minekazu Sakai ,  Tsuyoshi Fukada ,  Masakazu Terada ,  Shinsuke Watanabe ,  Minoru Nishida

发明人： Minekazu Sakai ,  Tsuyoshi Fukada ,  Masakazu Terada ,  Shinsuke Watanabe ,  Minoru Nishida

IPC分类号： G01P15/08 ,  B23P15/00

CPC分类号： G01P15/0802 ,  Y10S148/159

摘要： A method of producing a semiconductor dynamic sensor which features an improved sensitivity yet having a small size while avoiding damage to the thin distortion-producing portion. A resist film 49 is photo-patterned on the front main surface of the semiconductor substrate 41 except for the region where the upper isolation grooves are to be formed prior to forming the lower isolation groove 10 by the first etching of the back main surface of the semiconductor substrate 41 (which includes the epitaxial layer 42). Unlike the prior art, therefore, there is no need to spin-coat the front main surface of the semiconductor substrate 41 with the resist film 49 which is followed by photo-patterning after a predetermined region of the semiconductor substrate 41 has been reduced in thickness by the first etching. Therefore, damage therefore to the thin portion by the vacuum chucking the wafer during the spin-coating of the resist film is avoided.

摘要翻译： 一种制造半导体动态传感器的方法，其具有改善的灵敏度但具有小尺寸，同时避免对薄变形产生部分的损害。 在形成下隔离槽10之前，除了要形成上隔离槽的区域之外，在半导体基板41的前主表面上，通过第一次蚀刻 半导体衬底41（包括外延层42）。 因此，与现有技术不同，不需要在半导体基板41的预定区域的厚度减小之后用抗蚀剂膜49旋涂半导体基板41的前主表面，随后进行光图案化 通过第一次蚀刻。 因此，避免了在抗蚀剂膜的旋转涂覆期间通过夹紧晶片的真空对薄部的损伤。

公开(公告)号：US5063423A

公开(公告)日：1991-11-05

申请号：US567760

申请日：1990-08-15

申请人： Tetsuo Fujii ,  Minekazu Sakai ,  Akira Kuroyanagi

发明人： Tetsuo Fujii ,  Minekazu Sakai ,  Akira Kuroyanagi

IPC分类号： H01L21/28 ,  H01L29/788

CPC分类号： H01L21/28273 ,  H01L29/7883

摘要： A tunnel insulating film of a three-layer structure, wherein an oxide film is interposed between nitrided oxide films, is formed on the surface of a semiconductor substrate. A first polysilicon film serving as a low-concentration impurity region is formed on the tunnel insulating film. An oxide film is formed on that region of the first polysilicon film, which corresponds to the tunnel insulating film, the oxide film having such a thickness that the film can serve as a stopper for impurity diffusion and can allow electrons to pass through. A second polysilicon film, having an impurity concentration higher than that of the first polysilicon film, is formed on the oxide film. The first and second polysilicon films constitute a floating gate. A third polysilicon film serving as a control gate is formed above the second polysilicon film, with an insulating layer interposed therebetween.

摘要翻译： 在半导体衬底的表面上形成三层结构的隧道绝缘膜，其中在氮化氧化物膜之间插入氧化膜。 在隧道绝缘膜上形成用作低浓度杂质区的第一多晶硅膜。 在第一多晶硅膜的与隧道绝缘膜相对应的区域上形成氧化膜，氧化膜具有使膜能够作为用于杂质扩散的阻挡层的厚度，并且可以使电子通过。 在氧化膜上形成杂质浓度高于第一多晶硅膜的第二多晶硅膜。 第一和第二多晶硅膜构成浮栅。 用作控制栅极的第三多晶硅膜形成在第二多晶硅膜上方，绝缘层位于其间。

公开(公告)号：US5017979A

公开(公告)日：1991-05-21

申请号：US344605

申请日：1989-04-28

申请人： Tetsuo Fujii ,  Minekazu Sakai ,  Akira Kuroyanagi

发明人： Tetsuo Fujii ,  Minekazu Sakai ,  Akira Kuroyanagi

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/7883

摘要： A gate oxide film is formed on a surface of a semiconductor substrate. A tunnel insulating film having a thickness smaller than that of the gate insulating film is formed in a portion thereof corresponding to a tunnel region. A first silicon film having a low impurity concentration is formed on the gate insulating film. A second silicon film having an impurity concentration higher than that of the first silicon film is formed on the first silicon film so as to be connected thereto. A third silicon film is formed on the second silicon film through an insulating film. The second and third silicon films are formed into floating and control gates, respectively, thereby forming a semiconductor memory device.

摘要翻译： 在半导体衬底的表面上形成栅极氧化膜。 在对应于隧道区域的部分中形成厚度小于栅极绝缘膜厚度的隧道绝缘膜。 在栅极绝缘膜上形成杂质浓度低的第一硅膜。 在第一硅膜上形成杂质浓度高于第一硅膜的第二硅膜，以便与第一硅膜连接。 通过绝缘膜在第二硅膜上形成第三硅膜。 第二和第三硅膜分别形成浮动和控制栅极，从而形成半导体存储器件。