公开(公告)号：US20070282982A1

公开(公告)日：2007-12-06

申请号：US11422127

申请日：2006-06-05

申请人： Rhonda Childress ,  Oded Dubovsky ,  Itzhack Goldberg ,  Ido Levy ,  Ziv Rafalovich ,  Ramakrishnan Rajamony ,  Eric Van Hensbergen ,  Martin Tross

发明人： Rhonda Childress ,  Oded Dubovsky ,  Itzhack Goldberg ,  Ido Levy ,  Ziv Rafalovich ,  Ramakrishnan Rajamony ,  Eric Van Hensbergen ,  Martin Tross

IPC分类号： G06F15/173

CPC分类号： H04L41/0893

摘要： A system for policy-based management in a computer environment, the system including at least one rule configured to be applied to an element of a computer environment, at least one policy including at least one of the rules, at least one profile including at least one element of the computer environment, at least one association defining a relationship between one of the policies and one of the profiles, and a computer configured to instaniate any of the associations, thereby invoking any of the rules included in the related policy for application to any of the elements in the related profile.

摘要翻译： 一种用于计算机环境中用于基于策略的管理的系统，所述系统包括被配置为应用于计算机环境的元素的至少一个规则，包括至少一个规则的至少一个策略，至少一个简档至少包括 所述计算机环境的一个要素，至少一个关联，其定义所述策略中的一个与所述简档中的一个之间的关系;以及计算机，被配置为实现任何关联，从而调用包括在相关策略中的任何规则以应用于 相关资料中的任何元素。

公开(公告)号：US06499028B1

公开(公告)日：2002-12-24

申请号：US09282625

申请日：1999-03-31

申请人： Bishop Chapman Brock ,  Eli Chiprout ,  Elmootazbellah Nabil Elnozahy ,  David Brian Glasco ,  Ramakrishnan Rajamony ,  Freeman Leigh Rawson, III ,  Ronald Lynn Rockhold

发明人： Bishop Chapman Brock ,  Eli Chiprout ,  Elmootazbellah Nabil Elnozahy ,  David Brian Glasco ,  Ramakrishnan Rajamony ,  Freeman Leigh Rawson, III ,  Ronald Lynn Rockhold

IPC分类号： G06F1700

CPC分类号： G06F11/3409 ,  G06F11/3414 ,  G06F11/3471 ,  G06F11/3495 ,  G06F12/08 ,  G06F12/0813 ,  G06F2201/81 ,  G06F2201/86 ,  G06F2201/87 ,  G06F2201/88 ,  G06F2212/2542 ,  Y10S707/99934

摘要： A performance monitor configured to count memory transactions and to issue an interrupt to the computer system if the monitor detects a specified number of transactions associated with a particular segment of the physical address space of the system. The monitor includes an interface suitable for coupling to an interconnect network of a computer system and configured to extract physical address information from a transaction traversing the interconnect network, a translation module adapted for associating the extracted physical address with one of a plurality of memory blocks and, in response thereto, incrementing a memory block counter corresponding to the memory block, and an interrupt unit configured to assert an interrupt if the block counter exceeds a predetermined value. The interface unit is configurable to selectively monitor either incoming or outgoing transactions and the translation unit preferably includes a plurality of region filters each comprising one or more of the memory blocks. In the preferred embodiment, the plurality of block counters are implemented with a random access memory device. In one embodiment useful for simulating operation of the system and for checking the design of the performance monitor, the monitor further includes a transaction generator coupled to the interconnect network and configured to issue specified remote memory transactions at specified intervals if a monitor enable bit of the performance monitor is disabled. In one embodiment, the transaction generator is configurable to issue either outgoing transactions or incoming transactions.

摘要翻译： 如果监视器检测到与系统的物理地址空间的特定段相关联的指定数量的事务，则性能监视器被配置为对存储器事务进行计数并向计算机系统发出中断。 监视器包括适于耦合到计算机系统的互连网络并被配置为从穿过互连网络的事务提取物理地址信息的接口，适于将所提取的物理地址与多个存储器块中的一个相关联的翻译模块，以及 响应于此，增加对应于存储块的存储器块计数器，以及中断单元，被配置为在块计数器超过预定值时断言中断。 接口单元可配置为选择性地监视输入或输出事务，并且转换单元优选地包括多个区域滤波器，每个区域滤波器包括一个或多个存储器块。 在优选实施例中，多个块计数器由随机存取存储器件实现。 在一个实施例中有用于模拟系统的操作和用于检查性能监视器的设计，监视器还包括耦合到互连网络并被配置为以特定间隔发布指定的远程存储器事务的事务发生器，如果监视器使能位 性能监视器被禁用。 在一个实施例中，事务生成器可配置为发出传出事务或传入事务。

公开(公告)号：US06442654B1

公开(公告)日：2002-08-27

申请号：US09458406

申请日：1999-12-10

申请人： Bishop Chapman Brock ,  Eli Chiprout ,  Elmootazbellah Nabil Elnozahy ,  Ramakrishnan Rajamony ,  Freeman Leigh Rawson, III ,  Ronald Lynn Rockhold

发明人： Bishop Chapman Brock ,  Eli Chiprout ,  Elmootazbellah Nabil Elnozahy ,  Ramakrishnan Rajamony ,  Freeman Leigh Rawson, III ,  Ronald Lynn Rockhold

IPC分类号： G06F1200

CPC分类号： H04L67/2842

摘要： A system and method for providing in-server caching of shared data involves a server program that defines a server cache in RAM of a server machine and stores a selected file in the server cache. If a cached file is modified through the file system interface of the operating system of the server machine, the operating system automatically issues an upcall to the server program, the upcall identifying the modified file. In response to receipt of the upcall, the server program removes the modified file from the server cache. In one embodiment, the server program responds to a client request requiring access to a requested file by obtaining the requested file from the server cache if the server cache contains that file. Otherwise, the server program calls the operating system to obtain the requested file and then adds that file to the server cache as a cached file. The server program then generates a result based on the requested file and transmits the result to the remote data processing system.

摘要翻译： 用于提供共享数据的服务器间缓存的系统和方法涉及服务器程序，该服务器程序在服务器机器的RAM中定义服务器高速缓存，并将选定的文件存储在服务器高速缓存中。 如果通过服务器机器的操作系统的文件系统界面修改缓存的文件，则操作系统会自动向服务器程序发出一个上调，标识修改后的文件。 响应于接收到上调，服务器程序从服务器缓存中删除修改的文件。 在一个实施例中，如果服务器高速缓存包含该文件，服务器程序通过从服务器高速缓存获得所请求的文件来响应需要访问所请求文件的客户端请求。 否则，服务器程序会调用操作系统来获取所请求的文件，然后将该文件作为缓存文件添加到服务器缓存中。 然后，服务器程序基于所请求的文件生成结果，并将结果发送到远程数据处理系统。

公开(公告)号：US08543769B2

公开(公告)日：2013-09-24

申请号：US12509752

申请日：2009-07-27

申请人： Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

发明人： Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

IPC分类号： G06F12/00

CPC分类号： G06F12/084 ,  G06F12/0864 ,  G06F12/126 ,  Y02D10/13

摘要： A mechanism is provided in a virtual machine monitor for fine grained cache allocation in a shared cache. The mechanism partitions a cache tag into a most significant bit (MSB) portion and a least significant bit (LSB) portion. The MSB portion of the tags is shared among the cache lines in a set. The LSB portion of the tags is private, one per cache line. The mechanism allows software to set the MSB portion of tags in a cache to allocate sets of cache lines. The cache controller determines whether a cache line is locked based on the MSB portion of the tag.

摘要翻译： 在虚拟机监视器中提供了用于共享高速缓存中的细粒度高速缓存分配的机制。 该机制将高速缓存标签分成最高有效位（MSB）部分和最低有效位（LSB）部分。 标签的MSB部分在一组中的高速缓存行之间共享。 标签的LSB部分是私有的，每个缓存行一个。 该机制允许软件将缓存中的标签的MSB部分设置为分配高速缓存行集合。 高速缓存控制器基于标签的MSB部分来确定高速缓存行是否被锁定。

公开(公告)号：US08484307B2

公开(公告)日：2013-07-09

申请号：US12024397

申请日：2008-02-01

申请人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Robert S. Blackmore ,  Chulho Kim ,  Ramakrishnan Rajamony ,  William J. Starke ,  Hanhong Xue

发明人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Robert S. Blackmore ,  Chulho Kim ,  Ramakrishnan Rajamony ,  William J. Starke ,  Hanhong Xue

IPC分类号： G06F15/167 ,  G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F9/46

CPC分类号： G06F12/109 ,  G06F9/544

摘要： A data processing system enables global shared memory (GSM) operations across multiple nodes with a distributed EA-to-RA mapping of physical memory. Each node has a host fabric interface (HFI), which includes HFI windows that are assigned to at most one locally-executing task of a parallel job. The tasks perform parallel job execution, but map only a portion of the effective addresses (EAs) of the global address space to the local, real memory of the task's respective node. The HFI window tags all outgoing GSM operations (of the local task) with the job ID, and embeds the target node and HFI window IDs of the node at which the EA is memory mapped. The HFI window also enables processing of received GSM operations with valid EAs that are homed to the local real memory of the receiving node, while preventing processing of other received operations without a valid EA-to-RA local mapping.

摘要翻译： 数据处理系统通过物理内存的分布式EA-to-RA映射实现跨多个节点的全局共享存储（GSM）操作。 每个节点都有一个主机结构接口（HFI），它包括分配给并行作业最多一个本地执行任务的HFI窗口。 任务执行并行作业执行，但将全局地址空间的有效地址（EA）的一部分映射到任务相应节点的本地实际存储器。 HFI窗口使用作业ID对所有传出的GSM操作（本地任务）进行标记，并嵌入EA被映射到的节点的目标节点和HFI窗口ID。 HFI窗口还能够利用归属于接收节点的本地实际存储器的有效EA来处理接收的GSM操作，同时防止在没有有效的EA到RA本地映射的情况下处理其他接收到的操作。

公开(公告)号：US08239879B2

公开(公告)日：2012-08-07

申请号：US12024651

申请日：2008-02-01

申请人： Lakshminarayana B. Arimilli ,  Robert S. Blackmore ,  Gheorghe C. Cascaval ,  Ramakrishnan Rajamony

发明人： Lakshminarayana B. Arimilli ,  Robert S. Blackmore ,  Gheorghe C. Cascaval ,  Ramakrishnan Rajamony

IPC分类号： G06F3/00 ,  G06F13/00 ,  G06F15/167 ,  G06F9/46

CPC分类号： G06F9/544 ,  G06F9/542

摘要： A method for providing global notification of completion of a global shared memory (GSM) operation during processing by a target task executing at a target node of a distributed system. The distributed system has at least one other node on which an initiating task that generated the GSM operation is homed. The target task receives the GSM operation from the initiating task, via a host fabric interface (HFI) window assigned to the target task. The task initiates execution of the GSM operation on the target node. The task detects completion of the execution of the GSM operation on the target node, and issues a global notification to at least the initiating task. The global notification indicates the completion of the execution of the GSM operation to one or more tasks of a single job distributed across multiple processing nodes.

摘要翻译： 一种用于在由分布式系统的目标节点执行的目标任务的处理期间提供全局共享存储器（GSM）完成的全局通知的方法。 分布式系统具有至少一个其他节点，其上产生GSM操作的发起任务被归位。 目标任务通过分配给目标任务的主机结构接口（HFI）窗口从发起任务接收GSM操作。 该任务启动目标节点上的GSM操作的执行。 该任务检测目标节点上的GSM操作的执行完成，并向至少发起任务发出全局通知。 全局通知指示完成对多个处理节点分配的单个作业的一个或多个任务的GSM操作的执行。

公开(公告)号：US08185896B2

公开(公告)日：2012-05-22

申请号：US11845207

申请日：2007-08-27

申请人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Ramakrishnan Rajamony ,  Edward J. Seminaro ,  William E. Speight

发明人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Ramakrishnan Rajamony ,  Edward J. Seminaro ,  William E. Speight

IPC分类号： G06F9/46

CPC分类号： G06F9/5061 ,  G06F2209/5012

摘要： A method is provided for implementing a multi-tiered full-graph interconnect architecture. In order to implement a multi-tiered full-graph interconnect architecture, a plurality of processors are coupled to one another to create a plurality of processor books. The plurality of processor books are coupled together to create a plurality of supernodes. Then, the plurality of supernodes are coupled together to create the multi-tiered full-graph interconnect architecture. Data is then transmitted from one processor to another within the multi-tiered full-graph interconnect architecture based on an addressing scheme that specifies at least a supernode and a processor book associated with a target processor to which the data is to be transmitted.

摘要翻译： 提供了一种实现多层全图互连架构的方法。 为了实现多层全图互连架构，多个处理器彼此耦合以创建多个处理器书籍。 多个处理器书联接在一起以创建多个超节点。 然后，将多个超节点耦合在一起以创建多层全图互连体系结构。 然后，数据在多层全图互连体系结构中从一个处理器传输到另一个处理器，这是基于一个寻址方案，该寻址方案至少指定了一个与要发送数据的目标处理器相关联的超级节点和一个处理器。

公开(公告)号：US08140731B2

公开(公告)日：2012-03-20

申请号：US11845206

申请日：2007-08-27

申请人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Ramakrishnan Rajamony ,  Edward J. Seminaro ,  William E. Speight

发明人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Ramakrishnan Rajamony ,  Edward J. Seminaro ,  William E. Speight

IPC分类号： G06F13/14

CPC分类号： G06F15/16

摘要： A system is provided for implementing a multi-tiered full-graph interconnect architecture. In order to implement a multi-tiered full-graph interconnect architecture, a plurality of processors are coupled to one another to create a plurality of processor books. The plurality of processor books are coupled together to create a plurality of supernodes. Then, the plurality of supernodes are coupled together to create the multi-tiered full-graph interconnect architecture. Data is then transmitted from one processor to another within the multi-tiered full-graph interconnect architecture based on an addressing scheme that specifies at least a supernode and a processor book associated with a target processor to which the data is to be transmitted.

摘要翻译： 提供了一种用于实现多层全图互连架构的系统。 为了实现多层全图互连架构，多个处理器彼此耦合以创建多个处理器书籍。 多个处理器书联接在一起以创建多个超节点。 然后，将多个超节点耦合在一起以创建多层全图互连体系结构。 然后，数据在多层全图互连体系结构中从一个处理器传输到另一个处理器，这是基于一个寻址方案，该寻址方案至少指定了一个与要发送数据的目标处理器相关联的超级节点和一个处理器。

公开(公告)号：US08108545B2

公开(公告)日：2012-01-31

申请号：US11845227

申请日：2007-08-27

申请人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Ramakrishnan Rajamony

发明人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Ramakrishnan Rajamony

IPC分类号： G06F15/16 ,  G06F15/173 ,  H04L12/43 ,  H04L1/18

CPC分类号： H04L67/10 ,  H04L69/40

摘要： A mechanism is provided for packet coalescing in virtual channels of a data processing system. A first processor bundles original data into a data packet to be transmitted to a destination processor, the original data comprising payload data and overhead data. The first processor transmits the data packet to a second processor along a path to the destination processor. The second processor determines if the second processor has additional payload data destined for the same destination processor. Responsive to the second processor having the additional payload data, the second processor unbundles the data packet, adds the additional payload data to the payload data, and rebundles the payload data along with the additional payload data and the overhead data into a rebundled data packet. Then the second processor transmits the rebundled data packet to at least one other processor along the path to the destination processor.

摘要翻译： 提供了一种用于数据处理系统的虚拟通道中的分组聚合的机制。 第一处理器将原始数据捆绑到要发送到目的处理器的数据分组中，原始数据包括有效载荷数据和开销数据。 第一处理器沿着到目的地处理器的路径向第二处理器发送数据分组。 第二处理器确定第二处理器是否具有去往相同目的地处理器的附加有效载荷数据。 响应于具有附加有效载荷数据的第二处理器，第二处理器解除数据分组的捆绑，将附加的有效载荷数据添加到有效载荷数据，并将有效载荷数据连同额外的有效载荷数据和开销数据重新分组成重新绑定的数据分组。 然后，第二处理器将重新发送的数据分组传送到至少一个其他处理器，沿着到达目的地处理器的路径。

公开(公告)号：US07979617B2

公开(公告)日：2011-07-12

申请号：US12264764

申请日：2008-11-04

申请人： Paul E. McKenney ,  Benedict Jackson ,  Ramakrishnan Rajamony ,  Ronald L. Rockhold

发明人： Paul E. McKenney ,  Benedict Jackson ,  Ramakrishnan Rajamony ,  Ronald L. Rockhold

IPC分类号： G06F12/00

CPC分类号： G06F9/52

摘要： A method and computer system for efficiently handling high contention locking in a multiprocessor computer system. At least some of the processors in the system are organized into a hierarchy, and process an interruptible lock in response to the hierarchy. The method utilizes two alternative methods of acquiring the lock, including a conditional lock acquisition primitive and an unconditional lock acquisition primitive, and an unconditional lock release primitive for releasing the lock from a particular processor. To prevent races between processors requesting a lock acquisition and a processor releasing the lock, a release flag is utilized. Furthermore, in order to ensure that the a processor utilizing the unconditional lock acquisition primitive is granted the lock, a handoff flag is utilized.

摘要翻译： 一种用于在多处理器计算机系统中有效地处理高争用锁定的方法和计算机系统。 系统中的至少一些处理器被组织成层次结构，并响应层次结构处理可中断的锁。 该方法利用获取锁的两种替代方法，包括条件锁获取原语和无条件锁获取原语，以及用于从特定处理器释放锁的无条件锁释放原语。 为了防止请求锁获取的处理器和释放锁的处理器之间的比赛，利用释放标志。 此外，为了确保使用无条件锁定获取原语的处理器被授予锁定，则利用切换标志。