公开(公告)号：US06601149B1

公开(公告)日：2003-07-29

申请号：US09460831

申请日：1999-12-14

申请人： Bishop Chapman Brock ,  Eli Chiprout ,  Elmootazbellah Nabil Elnozahy ,  Ramakrishnan Rajamony ,  Freeman Leigh Rawson, III ,  Ronald Lynn Rockhold

发明人： Bishop Chapman Brock ,  Eli Chiprout ,  Elmootazbellah Nabil Elnozahy ,  Ramakrishnan Rajamony ,  Freeman Leigh Rawson, III ,  Ronald Lynn Rockhold

IPC分类号： G06F1300

CPC分类号： G06F11/323

摘要： A system for and method of monitoring memory transactions in a data processing system are disclosed. The method includes defining a set of memory transaction attributes with a monitoring system and detecting, on a data processing system connected to the monitoring system, memory transactions that match the defined set of memory transaction attributes. The number of detected memory transactions occurring during a specified duration are then displayed in a graphical format. In one embodiment, the data processing system comprises a non-uniform memory architecture (NUMA) system comprising a set of nodes. In this embodiment, the detected transactions comprise transactions passing through a switch connecting the nodes of the NUMA system. The set of memory transaction attributes may include memory transaction type information, node information, and transaction direction information. The data processing system may operate under a first operating system such as a Unix® based system while the monitoring system operates under a second operating system such as a Windows® operating system. The set of memory transactions may include memory address information. In this embodiment, defining the memory address information may include defining a memory window size, subdividing the memory window into a set of memory grains, and displaying the number of detected memory transactions corresponding to each memory grain in the memory window.

摘要翻译： 公开了一种在数据处理系统中监视存储器事务的系统和方法。 该方法包括使用监视系统定义一组存储器事务属性，并且在连接到监视系统的数据处理系统上检测与定义的存储器事务属性集匹配的存储器事务。 然后以图形格式显示在指定持续时间内发生的检测到的内存事务的数量。 在一个实施例中，数据处理系统包括包括一组节点的非均匀存储器架构（NUMA）系统。 在该实施例中，检测到的事务包括通过连接NUMA系统的节点的交换机的事务。 存储器事务属性集合可以包括存储器事务类型信息，节点信息和事务方向信息。 数据处理系统可以在诸如基于Unix的系统之类的第一操作系统下操作，同时监视系统在诸如Windows操作系统的第二操作系统下操作。 存储器事务的集合可以包括存储器地址信息。 在该实施例中，定义存储器地址信息可以包括定义存储器窗口大小，将存储器窗口细分成一组存储器晶粒，以及显示对应于存储器窗口中的每个存储器颗粒的检测到的存储器事务的数量。

公开(公告)号：US06499028B1

公开(公告)日：2002-12-24

申请号：US09282625

申请日：1999-03-31

申请人： Bishop Chapman Brock ,  Eli Chiprout ,  Elmootazbellah Nabil Elnozahy ,  David Brian Glasco ,  Ramakrishnan Rajamony ,  Freeman Leigh Rawson, III ,  Ronald Lynn Rockhold

发明人： Bishop Chapman Brock ,  Eli Chiprout ,  Elmootazbellah Nabil Elnozahy ,  David Brian Glasco ,  Ramakrishnan Rajamony ,  Freeman Leigh Rawson, III ,  Ronald Lynn Rockhold

IPC分类号： G06F1700

CPC分类号： G06F11/3409 ,  G06F11/3414 ,  G06F11/3471 ,  G06F11/3495 ,  G06F12/08 ,  G06F12/0813 ,  G06F2201/81 ,  G06F2201/86 ,  G06F2201/87 ,  G06F2201/88 ,  G06F2212/2542 ,  Y10S707/99934

摘要： A performance monitor configured to count memory transactions and to issue an interrupt to the computer system if the monitor detects a specified number of transactions associated with a particular segment of the physical address space of the system. The monitor includes an interface suitable for coupling to an interconnect network of a computer system and configured to extract physical address information from a transaction traversing the interconnect network, a translation module adapted for associating the extracted physical address with one of a plurality of memory blocks and, in response thereto, incrementing a memory block counter corresponding to the memory block, and an interrupt unit configured to assert an interrupt if the block counter exceeds a predetermined value. The interface unit is configurable to selectively monitor either incoming or outgoing transactions and the translation unit preferably includes a plurality of region filters each comprising one or more of the memory blocks. In the preferred embodiment, the plurality of block counters are implemented with a random access memory device. In one embodiment useful for simulating operation of the system and for checking the design of the performance monitor, the monitor further includes a transaction generator coupled to the interconnect network and configured to issue specified remote memory transactions at specified intervals if a monitor enable bit of the performance monitor is disabled. In one embodiment, the transaction generator is configurable to issue either outgoing transactions or incoming transactions.

摘要翻译： 如果监视器检测到与系统的物理地址空间的特定段相关联的指定数量的事务，则性能监视器被配置为对存储器事务进行计数并向计算机系统发出中断。 监视器包括适于耦合到计算机系统的互连网络并被配置为从穿过互连网络的事务提取物理地址信息的接口，适于将所提取的物理地址与多个存储器块中的一个相关联的翻译模块，以及 响应于此，增加对应于存储块的存储器块计数器，以及中断单元，被配置为在块计数器超过预定值时断言中断。 接口单元可配置为选择性地监视输入或输出事务，并且转换单元优选地包括多个区域滤波器，每个区域滤波器包括一个或多个存储器块。 在优选实施例中，多个块计数器由随机存取存储器件实现。 在一个实施例中有用于模拟系统的操作和用于检查性能监视器的设计，监视器还包括耦合到互连网络并被配置为以特定间隔发布指定的远程存储器事务的事务发生器，如果监视器使能位 性能监视器被禁用。 在一个实施例中，事务生成器可配置为发出传出事务或传入事务。

公开(公告)号：US06442654B1

公开(公告)日：2002-08-27

申请号：US09458406

申请日：1999-12-10

申请人： Bishop Chapman Brock ,  Eli Chiprout ,  Elmootazbellah Nabil Elnozahy ,  Ramakrishnan Rajamony ,  Freeman Leigh Rawson, III ,  Ronald Lynn Rockhold

发明人： Bishop Chapman Brock ,  Eli Chiprout ,  Elmootazbellah Nabil Elnozahy ,  Ramakrishnan Rajamony ,  Freeman Leigh Rawson, III ,  Ronald Lynn Rockhold

IPC分类号： G06F1200

CPC分类号： H04L67/2842

摘要： A system and method for providing in-server caching of shared data involves a server program that defines a server cache in RAM of a server machine and stores a selected file in the server cache. If a cached file is modified through the file system interface of the operating system of the server machine, the operating system automatically issues an upcall to the server program, the upcall identifying the modified file. In response to receipt of the upcall, the server program removes the modified file from the server cache. In one embodiment, the server program responds to a client request requiring access to a requested file by obtaining the requested file from the server cache if the server cache contains that file. Otherwise, the server program calls the operating system to obtain the requested file and then adds that file to the server cache as a cached file. The server program then generates a result based on the requested file and transmits the result to the remote data processing system.

摘要翻译： 用于提供共享数据的服务器间缓存的系统和方法涉及服务器程序，该服务器程序在服务器机器的RAM中定义服务器高速缓存，并将选定的文件存储在服务器高速缓存中。 如果通过服务器机器的操作系统的文件系统界面修改缓存的文件，则操作系统会自动向服务器程序发出一个上调，标识修改后的文件。 响应于接收到上调，服务器程序从服务器缓存中删除修改的文件。 在一个实施例中，如果服务器高速缓存包含该文件，服务器程序通过从服务器高速缓存获得所请求的文件来响应需要访问所请求文件的客户端请求。 否则，服务器程序会调用操作系统来获取所请求的文件，然后将该文件作为缓存文件添加到服务器缓存中。 然后，服务器程序基于所请求的文件生成结果，并将结果发送到远程数据处理系统。

公开(公告)号：US06349394B1

公开(公告)日：2002-02-19

申请号：US09282626

申请日：1999-03-31

申请人： Bishop Chapman Brock ,  Eli Chiprout ,  Elmootazbellah Nabil Elnozahy ,  David Brian Glasco ,  Ramakrishnan Rajamony ,  Freeman Leigh Rawson, III ,  Ronald Lynn Rockhold

发明人： Bishop Chapman Brock ,  Eli Chiprout ,  Elmootazbellah Nabil Elnozahy ,  David Brian Glasco ,  Ramakrishnan Rajamony ,  Freeman Leigh Rawson, III ,  Ronald Lynn Rockhold

IPC分类号： G06F1100

CPC分类号： G06F11/3471 ,  G06F11/302 ,  G06F11/3072 ,  G06F11/349 ,  G06F2201/87 ,  G06F2201/88

摘要： A performance monitor for a computer system that includes an interface, a filter module, and an address mapping module. The interface is suitable for coupling to an interconnect network of the computer system. The interconnect network links a local node of the system with at least one remote node of the system. The interface is configured to extract physical address information from a transaction traversing the interconnect network. The filter module associates the physical address with one of several memory blocks, where each memory block comprises a contiguous portion of the system's physical address space. The address mapping module associates the identified memory block with at least one range of virtual addresses associated with at least one of a plurality of concurrently executing programs and increments each of a set of access counters. The association between the selected memory block and the access counters is facilitated by a pointer field corresponding to the memory block.

摘要翻译： 包括接口，过滤器模块和地址映射模块的计算机系统的性能监视器。 该接口适用于耦合到计算机系统的互连网络。 互连网络将系统的本地节点与系统的至少一个远程节点连接。 该接口被配置为从穿过互连网络的事务提取物理地址信息。 滤波器模块将物理地址与几个存储器块之一相关联，其中每个存储器块包括系统的物理地址空间的连续部分。 地址映射模块将所识别的存储器块与至少一个与多个并发执行程序中的至少一个相关联的虚拟地址范围进行关联，并增加一组访问计数器的每一个。 所选择的存储块和存取计数器之间的关联由对应于存储块的指针字段来促进。

公开(公告)号：US06473085B1

公开(公告)日：2002-10-29

申请号：US09465295

申请日：1999-12-17

申请人： Bishop Chapman Brock ,  Eli Chiprout ,  Elmootazebllah Nabil Elinozahy ,  Ramakrishnan Rajamony ,  Freeman Leigh Rawson, III ,  Ronald Lynn Rockhold

发明人： Bishop Chapman Brock ,  Eli Chiprout ,  Elmootazebllah Nabil Elinozahy ,  Ramakrishnan Rajamony ,  Freeman Leigh Rawson, III ,  Ronald Lynn Rockhold

IPC分类号： G06F1516

CPC分类号： G06T15/00

摘要： A method and system for optimizing image quality while operating an interactive graphics application within a data processing system. First, the image rendering speed for each of the rendering modes available within the interactive graphics application are assessed. Upon initial operation of the interactive graphics system, a default rendering mode is activated. During operation of the interactive graphics application, the processing load imposed on the data processing system is monitored and utilized as a user activity metric. The active rendering mode is updated in accordance with the user activity metric, such that the speed of the selected rendering mode varies inversely with the current processing load.

摘要翻译： 一种用于在数据处理系统内操作交互式图形应用程序时优化图像质量的方法和系统。 首先，评估交互式图形应用中可用的每个呈现模式的图像呈现速度。 在交互式图形系统的初始操作时，默认渲染模式被激活。 在交互式图形应用的操作期间，对数据处理系统施加的处理负荷被监视并用作用户活动度量。 主动渲染模式根据用户活动度量被更新，使得所选渲染模式的速度与当前处理负载成反比变化。

公开(公告)号：US08370517B2

公开(公告)日：2013-02-05

申请号：US09965013

申请日：2001-09-27

申请人： Patrick Joseph Bohrer ,  Bishop Chapman Brock ,  Elmootazbellah Nabil Elnozahy ,  Ramakrishnan Rajamony ,  Freeman Leigh Rawson, III

发明人： Patrick Joseph Bohrer ,  Bishop Chapman Brock ,  Elmootazbellah Nabil Elnozahy ,  Ramakrishnan Rajamony ,  Freeman Leigh Rawson, III

IPC分类号： G06F15/16

CPC分类号： G06F1/3203 ,  G06F1/324 ,  H04L29/06 ,  H04L67/1002 ,  H04L67/1008 ,  H04L67/1014 ,  H04L67/1029 ,  H04L67/1031 ,  H04L69/24 ,  H04L69/329 ,  Y02D10/126

摘要： A data processing network and method for conserving energy in which an initial negotiation between a network server and a switch to which the server is connected is performed to establish an initial operating frequency of the server-switch link. An effective data rate of the server is determined based on network traffic at the server. Responsive to determining that the effective data rate is materially different than the current operating frequency, a subsequent negotiation is performed to establish a modified operating frequency where the modified operating frequency is closer to the effective data rate than the initial operating frequency. The determination of the effective date rate and the contingent initiation of a subsequent negotiation may be repeated periodically during the operating of the network. In one embodiment, the initial and subsequent negotiation are compliant with the IEEE 802.3 standard.

公开(公告)号：US06421775B1

公开(公告)日：2002-07-16

申请号：US09335301

申请日：1999-06-17

申请人： Bishop Chapman Brock ,  David Brian Glasco ,  James Lyle Peterson ,  Ramakrishnan Rajamony ,  Ronald Lynn Rockhold

发明人： Bishop Chapman Brock ,  David Brian Glasco ,  James Lyle Peterson ,  Ramakrishnan Rajamony ,  Ronald Lynn Rockhold

IPC分类号： G06F15177

CPC分类号： G06F15/177

摘要： A data processing system includes a plurality of processing nodes that each contain at least one processor and data storage. The plurality of processing nodes are coupled together by a system interconnect. The data processing system further includes a configuration utility residing in data storage within at least one of the plurality of processing nodes. The configuration utility selectively configures the plurality of processing nodes into either a single non-uniform memory access (NUMA) system or into multiple independent data processing systems through communication via the system interconnect.

摘要翻译： 数据处理系统包括多个处理节点，每个处理节点包含至少一个处理器和数据存储器。 多个处理节点通过系统互连耦合在一起。 数据处理系统还包括驻留在多个处理节点中的至少一个处理节点内的数据存储器中的配置实用程序。 配置实用程序通过经由系统互连的通信将多个处理节点选择性地配置为单个非均匀存储器访问（NUMA）系统或多个独立的数据处理系统。

公开(公告)号：US06836849B2

公开(公告)日：2004-12-28

申请号：US09826986

申请日：2001-04-05

申请人： Bishop Chapman Brock ,  Harm Peter Hofstee ,  Mark A. Johnson ,  Thomas Walter Keller, Jr. ,  Kevin John Nowka

发明人： Bishop Chapman Brock ,  Harm Peter Hofstee ,  Mark A. Johnson ,  Thomas Walter Keller, Jr. ,  Kevin John Nowka

IPC分类号： G06F126

CPC分类号： G06F1/3203

摘要： A method and controller for managing power and performance of a multiprocessor (MP) system is described. The controller receives sensor data corresponding to physical parameters within the MP system. The controller also receives quality of service and policy parameters corresponding to the MP system. The quality of service parameters define commitments to customers for utilization of the MP system. The policy parameters correspond to operation limits on inputs and outputs of the MP system. The operation input limits relate to the cost and availability of power or individual processor availability. The operation output limits relate to the amount of heat, acoustic noise levels, EMC levels, etc. that the individual or group of processors in the MP system are allowed to generate in a particular environment. A controller receives the physical parameters, the quality of service parameters and policy parameters and determines performance goals for the MP system and processors within the MP system. Then controller generates controls and applies them to individual processors to achieve the performance goals.

摘要翻译： 描述了一种用于管理多处理器（MP）系统的功率和性能的方法和控制器。 控制器接收与MP系统内的物理参数对应的传感器数据。 控制器还接收与MP系统对应的服务质量和策略参数。 服务质量参数定义了对客户使用MP系统的承诺。 策略参数对应于MP系统的输入和输出的操作限制。 操作输入限制涉及功率或单个处理器可用性的成本和可用性。 操作输出限制涉及允许MP系统中的个体或一组处理器在特定环境中生成的热量，声学噪声水平，EMC等级等。 控制器接收物理参数，服务质量参数和策略参数，并确定MP系统中的MP系统和处理器的性能目标。 然后控制器生成控件并将其应用于各个处理器以实现性能目标。

公开(公告)号：US06886106B2

公开(公告)日：2005-04-26

申请号：US09978358

申请日：2001-10-16

申请人： Bishop Chapman Brock ,  Gary Dale Carpenter ,  Amanda Christine Caswell ,  Eric William MacDonald ,  Timothy Joe Rubidoux

发明人： Bishop Chapman Brock ,  Gary Dale Carpenter ,  Amanda Christine Caswell ,  Eric William MacDonald ,  Timothy Joe Rubidoux

IPC分类号： G06F1/08 ,  G06F1/04 ,  G06F1/32 ,  H03K3/017

CPC分类号： G06F1/08

摘要： A method and apparatus for providing a dynamically alterable output clock from an input clock based on the value of an integer, where the integer can be modified continuously. The invention also provides a sample cycle output which is an enable pulse, having the width of the input clock cycle, that is asserted one or two input clock cycles prior to the rising edge alignment of the input and output clocks, that acts as a rising edge alignment enable signal, maintaining a one-to-one correspondence between the sample cycle assertions and rising edge alignment events, regardless of the dynamic changes in the value of the integer.

摘要翻译： 一种用于基于整数的值从输入时钟提供动态可变输出时钟的方法和装置，其中整数可以连续地修改。 本发明还提供了采样周期输出，其是具有输入时钟周期的宽度的使能脉冲，其在输入和输出时钟的上升沿对准之前被断言为一个或两个输入时钟周期，其作为上升沿 边缘对齐使能信号，在采样周期断言和上升沿对齐事件之间保持一一对应，而不管整数值的动态变化。

公开(公告)号：US06662251B2

公开(公告)日：2003-12-09

申请号：US09817089

申请日：2001-03-26

申请人： Bishop Chapman Brock ,  Gary Dale Carpenter

发明人： Bishop Chapman Brock ,  Gary Dale Carpenter

IPC分类号： G06F1300

CPC分类号： G06F13/364

摘要： A system in which bus signals are selectively modified to effectively isolate desired bus agents from the bus. The selective modification of bus signals may be determined from a stored table (permission table) indicating permitted and prohibited bus transaction initiator/target pairs. The permission table may be located in a dedicated device, such as a programmable logic array or application specific integrated circuit. Alternatively, the permission table may be integrated into the bus arbiter. The permission table may be used to provide a unique 1-bit signal to each bus agent indicating whether the corresponding bus agent is permitted to receive transactions from the current bus master. The permission bit may be routed to external gating circuitry associated with each bus agent. The gating circuitry may receive one or more bus control signals and may modify the control signals depending upon the state of the permission bit. In an embodiment in which the bus is a PCI bus, the gating circuitry may receive the FRAME# and GNT# signals for each bus agent.