公开(公告)号：US09178690B2

公开(公告)日：2015-11-03

申请号：US14252450

申请日：2014-04-14

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: H04L7/00 ,  H04L7/033 ,  H04L5/00 ,  H04L25/14 ,  H04L25/49

CPC classification number: H04L7/0337 ,  H04L5/0053 ,  H04L7/0012 ,  H04L7/0087 ,  H04L7/033 ,  H04L25/14 ,  H04L25/49 ,  H04L25/4923

Abstract: System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. Each symbol in a sequence of symbols received from a plurality of signal wires is received in an odd transmission interval or an even transmission interval. A first clock signal is generated from transitions in signaling state of the wires occurring between each odd transmission interval and a consecutive even transmission interval. A second clock signal is generated from transitions in signaling state of the plurality of wires occurring between each even transmission interval and a consecutive odd transmission interval. The first and second clock signals are used to capture symbols received in even and odd transmission intervals, respectively.

Abstract translation: 描述了便于通过多线数据通信链路，特别是在电子设备内的两个设备之间传输数据的系统，方法和装置。 在多个信号线中接收的符号序列中的每个符号以奇数传输间隔或偶数传输间隔被接收。 在每个奇数传输间隔和连续偶数传输间隔之间发生的布线的信令状态的转换产生第一时钟信号。 第二时钟信号由在每个偶数传输间隔和连续的奇数传输间隔之间发生的多条线的信令状态的转换产生。 第一和第二时钟信号分别用于捕获在偶数和奇数传输间隔中接收的符号。

公开(公告)号：US20150286606A1

公开(公告)日：2015-10-08

申请号：US14243459

申请日：2014-04-02

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: G06F13/42 ,  G06F13/364

CPC classification number: G06F13/4291 ,  G06F13/364 ,  G06F13/42 ,  G06F13/4282 ,  H04L12/6418

Abstract: System, methods and apparatus are described that offer improved performance of an Inter-Integrated Circuit (I2C) bus. Primary data may be encoded in first signaling in accordance with I2C bus protocols, and the first signaling may be combined with second signaling to obtain combined signaling for transmission on an I2C bus. Secondary data may be encoded in the second signaling with the combined signaling remaining compatible with the I2C bus protocols. The second signaling may modulate a voltage level of at least one signal in the first signaling. The second signaling may pulse-width modulate a clock signal transmitted on the I2C bus. The second signaling may modify a start condition between bytes transmitted on the I2C bus. The second signaling may add a plurality of short pulses to a clock signal transmitted in the first signaling.

公开(公告)号：US20150263823A1

公开(公告)日：2015-09-17

申请号：US14214285

申请日：2014-03-14

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: H04L1/00 ,  H03M13/05

CPC classification number: H04L1/0041 ,  G06F13/40 ,  H03M5/14 ,  H03M13/05 ,  H03M13/31 ,  H04L1/0042 ,  H04L1/0057 ,  H04L25/0272 ,  H04L25/14 ,  H04L2001/0094

Abstract: System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A data payload may be converted to a set of transition numbers, the transition numbers may be converted to a sequence of symbols and an error correction code (ECC) may be calculated from symbols in the sequence of symbols. The ECC corresponds to the data payload and the ECC may be appended to the data payload such that the set of transition numbers includes transition numbers corresponding to the ECC. The sequence of symbols is then transmitted on a plurality of signal wires. Clock information is encoded in the sequence of symbols. The clock information may be encoded by ensuring that each pair of consecutive symbols in the sequence of symbols includes two symbols that produce different signaling states on the plurality of signal wires.

Abstract translation: 描述了便于通过多线数据通信链路，特别是在电子设备内的两个设备之间传输数据的系统，方法和装置。 可以将数据有效载荷转换成一组转换号码，转换号码可以被转换成符号序列，并且可以从符号序列中的符号计算纠错码（ECC）。 ECC对应于数据有效载荷，并且ECC可以附加到数据有效载荷，使得该组转换号包括对应于ECC的转移号。 然后，在多条信号线上发送符号序列。 时钟信息以符号序列编码。 可以通过确保符号序列中的每对连续符号包括在多条信号线上产生不同信令状态的两个符号来编码时钟信息。

公开(公告)号：US09118457B2

公开(公告)日：2015-08-25

申请号：US14205242

申请日：2014-03-11

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Joseph Cheung

IPC: H04L7/00 ,  H04L7/027 ,  G06F13/40 ,  G06F13/42 ,  H04L25/14

CPC classification number: H04L7/027 ,  G06F13/4072 ,  G06F13/4295 ,  H04L25/00 ,  H04L25/14

Abstract: System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A sequence of data bits is converted into M transition numbers, which are then converted into a sequence of symbols. The sequence of symbols is transmitted received over N wires. A clock signal may be effectively embedded in the transmission of the sequence of symbols. Each of the sequence of symbols may be selected based on a corresponding one of the M transition numbers and a value of a preceding one of the sequence of symbols.

Abstract translation: 描述了便于通过多线数据通信链路，特别是在电子设备内的两个设备之间传输数据的系统，方法和装置。 数据比特序列被转换成M个转换号码，然后转换成符号序列。 通过N线接收符号序列。 可以有效地将时钟信号嵌入到符号序列的传输中。 符号序列中的每一个可以基于M个转移号码中的一个和符号序列中的前一个的值来选择。

公开(公告)号：US20150234773A1

公开(公告)日：2015-08-20

申请号：US14625567

申请日：2015-02-18

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: G06F13/42

CPC classification number: G06F13/4291 ,  G06F13/4221 ,  G06F13/4295

Abstract: A device may include an interface to couple to a multi-mode bus shared with one or more I2C-compatible devices. The bus may include a first line and a second line, wherein in a first mode of operation the first line transmits data and the second line transmits a clock, while in a second mode of operation the first and second lines are both used to transmit data. The device may also include a transmitter to transmit data over the bus (SDA line 3204 and SCL line 3206) as a sequence of pulses within symbol slots. In the second mode of operation a transmission period of a first symbol slot is stretched to prevent the I2C-compatible devices from changing into an unpredictable state as a result of a transition from a first pulse to a second pulse.

Abstract translation: 设备可以包括耦合到与一个或多个I2C兼容设备共享的多模总线的接口。 总线可以包括第一行和第二行，其中在第一操作模式中，第一行发送数据，第二行发送时钟，而在第二操作模式中，第一和第二行都用于传送数据 。 该装置还可以包括发送器，用于通过总线（SDA线3204和SCL线3206）发送数据作为符号时隙内的脉冲序列。 在第二操作模式中，延长了第一符号时隙的传输周期，以防止由于从第一脉冲到第二脉冲的转变而使I2C兼容设备变为不可预测状态。

公开(公告)号：US20150098536A1

公开(公告)日：2015-04-09

申请号：US14252450

申请日：2014-04-14

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: H04L7/033 ,  H04L7/00 ,  H04L5/00

CPC classification number: H04L7/0337 ,  H04L5/0053 ,  H04L7/0012 ,  H04L7/0087 ,  H04L7/033 ,  H04L25/14 ,  H04L25/49 ,  H04L25/4923

Abstract: System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. Each symbol in a sequence of symbols received from a plurality of signal wires is received in an odd transmission interval or an even transmission interval. A first clock signal is generated from transitions in signaling state of the wires occurring between each odd transmission interval and a consecutive even transmission interval. A second clock signal is generated from transitions in signaling state of the plurality of wires occurring between each even transmission interval and a consecutive odd transmission interval. The first and second clock signals are used to capture symbols received in even and odd transmission intervals, respectively.

Abstract translation: 描述了便于通过多线数据通信链路，特别是在电子设备内的两个设备之间传输数据的系统，方法和装置。 在多个信号线中接收的符号序列中的每个符号以奇数传输间隔或偶数传输间隔被接收。 在每个奇数传输间隔和连续偶数传输间隔之间发生的布线的信令状态的转换产生第一时钟信号。 第二时钟信号由在每个偶数传输间隔和连续的奇数传输间隔之间发生的多条线的信令状态的转换产生。 第一和第二时钟信号分别用于捕获在偶数和奇数传输间隔中接收的符号。

公开(公告)号：US08970248B2

公开(公告)日：2015-03-03

申请号：US14210246

申请日：2014-03-13

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Chulkyu Lee ,  Joseph Cheung

IPC: H03K17/16 ,  H04L27/20 ,  G06F13/40 ,  G08C19/00 ,  H04B1/06 ,  H04B3/00 ,  H04L25/02 ,  H04L29/06

CPC classification number: H04L27/2071 ,  G06F13/4063 ,  G08C19/00 ,  H04B1/06 ,  H04B3/00 ,  H04L25/0272 ,  H04L25/0292 ,  H04L69/18

Abstract: A termination network for a receiver device is provided to support both D-PHY signaling and N-factorial signaling. The first end of each of a plurality dynamically configurable switches is coupled to a common node. A first end of each of a plurality of resistances is coupled to a second end of a corresponding switch. A plurality of terminals receive differential signals and each terminal is coupled to a corresponding second end of a resistance. Each of a plurality differential receivers is coupled between two terminals of the termination network, wherein a first differential receiver and a second differential receiver are coupled to the same two terminals, the first differential receiver is used when the differential signals use a first type of differential signal encoding, the second differential receiver is used when the differential signals use a second type of differential signal encoding.

Abstract translation: 提供用于接收机设备的终端网络以支持D-PHY信令和N阶因子信令。 多个动态可配置开关中的每一个的第一端耦合到公共节点。 多个电阻中的每一个的第一端耦合到相应开关的第二端。 多个端子接收差分信号，并且每个端子耦合到电阻的对应的第二端。 多个差分接收器中的每一个耦合在终端网络的两个终端之间，其中第一差分接收机和第二差分接收机耦合到相同的两个终端，当差分信号使用第一类型的差分时，使用第一差分接收机 信号编码时，当差分信号使用第二类型的差分信号编码时，使用第二差分接收机。

公开(公告)号：US20140372644A1

公开(公告)日：2014-12-18

申请号：US14302365

申请日：2014-06-11

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Joseph Cheung

IPC: G06F13/42 ,  G06F13/364

CPC classification number: G06F13/4291 ,  G06F13/364 ,  G06F13/4282 ,  G06F13/4295 ,  H04L7/0331

Abstract: System, methods and apparatus are described that include a serial bus, including a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. The bus has a first line and a second line, a first set of devices coupled to the bus and a second set of devices coupled to the bus. A method of operating the bus includes configuring the first set of devices to use the first line for data transmissions and use the second line for a first clock signal in a first mode of operation, and configuring the second set of devices to use both the first line and the second line for data transmissions while embedding a second clock signal within symbol transitions of the data transmissions in a second mode of operation.

Abstract translation: 描述了包括串行总线的系统，方法和装置，其包括用于互联集成电路（I2C）和/或相机控制接口（CCI）操作的串行总线。 总线具有第一线路和第二线路，耦合到总线的第一组设备和耦合到总线的第二组设备。 操作总线的方法包括配置第一组设备以使用第一行进行数据传输，并且在第一操作模式中使用第二行作为第一时钟信号，并且将第二组设备配置为使用第一组 线和用于数据传输的第二行，同时在第二操作模式中将第二时钟信号嵌入在数据传输的符号转换内。

公开(公告)号：US20140254712A1

公开(公告)日：2014-09-11

申请号：US14199064

申请日：2014-03-06

Applicant: QUALCOMM Incorporated

Inventor： Chulkyu Lee ,  George Alan Wiley ,  Shoichiro Sengoku

IPC: H04B3/06

CPC classification number: H04B3/06 ,  G06F13/4072 ,  Y02D10/14 ,  Y02D10/151

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. Transmission lines are selectively terminated in an N-phase polarity encoded transmitter when the transmission lines would otherwise be undriven. Data is mapped to a sequence of symbols to be transmitted on a plurality of wires. The sequence of symbols is encoded in three signals. Each of the three terminals may be driven such that transistors are activated to couple a terminal to first and second voltage levels through a pair of impedances when the terminal would otherwise be undriven. The terminal is then pulled toward an intermediate voltage level while the terminal presents a desired impedance level to a transmission line.

Abstract translation: 描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个设备之间。 当传输线否则将被驱动时，传输线选择性地终止在N相极性编码的发射机中。 数据被映射到要在多根线上传输的符号序列。 符号序列被编码为三个信号。 可以驱动三个端子中的每一个，使得晶体管被激活以在端子否则将不被引导时通过一对阻抗将端子耦合到第一和第二电压电平。 然后将终端拉向中间电压电平，同时终端向传输线呈现期望的阻抗电平。

公开(公告)号：US10484164B2

公开(公告)日：2019-11-19

申请号：US16243647

申请日：2019-01-09

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: H04L25/49 ,  H04L7/00 ,  H04L7/033 ,  H03K5/13 ,  H03K5/1534 ,  G06F1/12 ,  H03K5/133

Abstract: A method and an apparatus are provided. The apparatus may include a clock recovery circuit having a plurality of input latches configured to assume a first state when a first pulse is received in one or more of a plurality of input signals, combinational logic configured to provide a second pulse response to the first pulse, a delay circuit configured to produce a third pulse on a receive clock that is delayed with respect to the second pulse, a plurality of output flip-flops configured to capture the first state when triggered by the third pulse. The first state may identify which of the plurality of input signals received input pulses.